• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.410.1-410.1
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• 2014

A soft-lithographic top-down approach is combined with an epitaxial layer transfer process to fabricate high quality III-V compound semiconductor nanowires (NWs) and integrate them on Si/SiO2 substrates, using MBE-grown ultrathin InAs as a source wafer. The channel width of the InAs nanowires is controlled by using solvent-assisted nanoscale embossing (SANE), descumming, and etching processes. By optimizing these processes, the NW width is scaled to less than 50 nm, and the InAs NWFETs has ${\sim}1,600cm^2/Vs$ peak electron mobility, which indicates no mobility degradation due to the size.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.359-362
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• 2010

In this study, inverter logic circuits on a plastic substrate are built with two top-gate FETs in series on a single ZnO nanowire. The voltage transfer characteristics of the ZnO nanowire-based inverter logic circuit exhibit a clear inverting operation. The logic swing, gain and transition width of the inverter logic circuit is about 90 %, 1.03 and 1.2 V, respectively. The result of mechanical bending cycles of the inverter logic circuit on a plastic substrate shows that the stable performance is maintained even after many hundreds of bending cycles.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.33-33
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• 2009

Silicon nano-structures have great potential in bionic sensor applications. Atomic force microscopy (AFM) anodic oxidation have many advantages for the nanostructure fabrication, such as simple process in atmosphere at room temperature, compatibility with conventional Si process. In this work, we fabricated simple FET structures with channel width W~ 10nm (nanowire) and $1{\mu}m$ (nano-ribbon) on ~10, 20 and 100nm-thinned silicon-on-insulator (SOI) wafers in order to investigate the surface effect on the transport characteristics of nano-channel. For further quantitative analysis, we carried out the 2D numerical simulations to investigate the effect of channel surface states on the carrier distribution behavior inside the channel. The simulated 2D cross-sectional structures of fabricated devices had channel heights of H ~ 10, 20, and 100nm, widths of L ~ $1{\mu}m$ and 10nm respectively, where we simultaneously varied the channel surface charge density from $1{\times}10^{-9}$ to $1{\times}10^{-7}C/cm2$. It has been shown that the side-wall charge of nanowire channel mainly affect the I-V characteristics and this was confirmed by the 2D numerical simulations.

• Transactions on Electrical and Electronic Materials
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• v.14 no.3
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• pp.139-142
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• 2013

Silicon nanowire (SiNW) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices were fabricated and their electrical characteristics were analyzed. Compared to planar SONOS devices, these SiNW SONOS devices have good program/erase (P/E) characteristics and a large threshold voltage ($V_T$) shift of 2.5 V in 1ms using a gate pulse of +14 V. The devices also show excellent immunity to short channel effects (SCEs) due to enhanced gate controllability, which becomes more apparent as the nanowire width decreases. This is attributed to the fully depleted mode operation as the nanowire becomes narrower. 3D TCAD simulations of both devices show that the electric field of the junction area is significantly reduced in the SiNW structure.

• Journal of the Korean Ceramic Society
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• v.45 no.4
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• pp.191-195
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• 2008

Highly ordered silver nanowire with a diameter of 10 nm was arrayed by electroless deposition in a porous anodic aluminum oxide(AAO) membrane. The AAO membrane was fabricated electrochemically in an oxalic acid solution via a two-step anodization process, while growth of the silver nanowire was initiated by using electroless deposition at the long-range-ordered nanochannels of the AAO membrane followed by thermal reduction of a silver nitrate aqueous solution by increasing the temperature up to $350^{\circ}C$ for an hour. An additional electro-chemical procedure was applied after the two-step anodization to control the pore size and channel density of AAO, which enabled us to fabricate highly-ordered silver nanowire on a large scale. Electroless deposition of silver nitrate aqueous solution into the AAO membrane and thermal reduction of silver nanowires was performed by increasing the temperature up to $350^{\circ}C$ for 1 h. The morphologies of silver nanowires arrayed in the AAO membrane were investigated using SEM. The chemical composition and crystalline structure were confirmed by XRD and EDX. The electroless-deposited silver nanowires in AAO revealed a well-crystallized self-ordered array with a width of 10 nm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.9
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• pp.1771-1777
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• 2016

In this thesis, the breakdown voltage characteristics of silicon nanowire N-channel GAA MOSFETs were analyzed through experiments and 3-dimensional device simulation. GAA MOSFETs with the gate length of 250nm, the gate dielectrics thickness of 6nm and the channel width ranged from 400nm to 3.2um were used. The breakdown voltage was decreased with increasing gate voltage but it was increased at high gate voltage. The decrease of breakdown voltage with increasing channel width is believed due to the increased current gain of parasitic transistor, which was resulted from the increased potential in channel center through floating body effects. When the positive charge was trapped into the gate dielectrics after gate stress, the breakdown voltage was decreased due to the increased potential in channel center. When the negative charge was trapped into the gate dielectrics after gate stress, the breakdown voltage was increased due to the decreased potential in channel center. We confirmed that the measurement results were agreed with the device simulation results.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.9
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• pp.728-731
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• 2009

We report numerical simulations to investigate of the dependendce of the on/off current ratio and channel charge distributions in silicon nanowire (SiNW) field-effect transistors (FETs) on the channel width and thicknesses. In order to investigate the transport behavior in devices with different channel geometries, we have performed detailed two-dimensional simulations of SiNWFETs and control FETs with a fixed channel length L of $10\;{\mu}m$, but varying the channel width W from 5 nm to $5\;{\mu}m$, and thickness t from 10 nm to 30 nm. We have show that $Q_{ON}/Q_{OFF}$ drastically decreases (from $^{\sim}2.9{\times}10^4$ to $^{\sim}9.8{\times}10^3$) as the channel thickness increases (from 10 nm to 30 nm). As a result of the simulation using a quantum model, even higher charge density in the bottom of SiNW channel was observed then in the bottom of control channel.

• Journal of Magnetics
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• v.17 no.4
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• pp.242-244
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• 2012

We report on the basis of experiments that magnetic domain structures exhibit a transition between single and dendrite domains with respect to the width of ferromagnetic nanowires. This transition is directly observed in CoFe/Pt multilayered nanowires having a width in the range of 580 nm to 4.2 ${\mu}m$ with a magnetic force microscope. Nanowires wider than 1.5 ${\mu}m$ show typical dendrite domain patterns, whereas the nanowires narrower than 690 nm exhibit single domain patterns. The transition occurs gradually between these widths, which are similar to the typical widths of the dendrite domains. Such a transition affects the strength of the domain wall propagation field; this finding was made by using a time-resolved magneto-optical Kerr effect microscope, and shows that the domain wall dynamics also exhibit a transition in accordance with the domain configuration.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.564-564
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• 2012

Graphene has been emerged as a fascinating material for future nanoelectronic applications due to its extraordinally electronic properties. However, their zero-bandgap semimetallic nature is a major problem for applications in high performance field-effect transistors (FETs). Graphene nanoribbons (GNRs) with narrow widths (${\geq}10nm$) exhibit semiconducting behavior, which can be used to overcome this problem. In previous reports, GNRs were produced by several approaches, such as electron beam lithography patterning, chemically derived GNRs, longitudinal unzipping of carbon nanotubes, and inorganic nanowire template. Using these methods, however, the width distribution of GNRs was a quiet broad and substantial defects were inevitably occurred. Here, we report a novel approach for fabricating width-tailored GNRs by focused ion beam-assisted chemical vapor deposition (FIB-CVD). Width-tailored phenanthrene ($C_{14}H_{10}$) templates for direct growth of GNRs were prepared on $SiO_2$/Si substrate by FIB-CVD. The GNRs on the templates were synthesized at $900-1,050^{\circ}C$ with introducing $CH_4$ $(20sccm)/H_2$ (10 sccm) mixture gas for 10-300 min. Structural characterizations of the GNRs were carried out using Raman spectroscopy, scanning electron microscopy, and atomic force microscopy.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.38 no.8
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• pp.893-898
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• 2014

A direct pulsed laser process for welding and networking silver nanowires was developed. The welded nanowire network demonstrated modified electrical properties in a transparent substance. In particular, the welding points on the nanowires were investigated to measure the resistance at the connections. The level of networking in nanowires was explored with respect to various laser pulse widths and average power densities. In particular, the influence of laser beam density was investigated in detail. Selective laser treatment can be advantageous in imparting customized local property changes in transparent conducting materials. Various applications of the process are also discussed in this paper.