• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2015년도 추계학술대회
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• pp.889-893
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• 2015

본 연구에서는 채널 폭 변화에 따른 나노와이어 GAA 소자의 GIDL 전류 (Gate Induced Drain Leakage Current)를 측정하고, hot carrier 스트레스를 인가하였을 때 소자의 GIDL전류특성 변화를 분석하였다. 소자의 길이는 250nm로 고정시키고 채널 폭이 10nm, 50nm, 80nm, 130nm인 소자들을 사용하여 측정하였다. 스트레스 전의 소자를 측정한 결과 채널 폭이 감소할수록 GIDL전류가 증가하였고, 채널 폭이 증가할수록 구동전류는 증가함을 확인하였다. Hot carrier 스트레스에 따른 GIDL 전류 측정값의 변화율은 채널 폭이 감소할수록 큰 변화율을 보였다. 또한, 채널 폭이 감소할수록 또 hot carrier 스트레스 후 GIDL 전류가 증가하는 이유를 소자 시뮬레이션을 통하여 확인하였다.

• Journal of Magnetics
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• 제13권4호
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• pp.136-139
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• 2008

A simplified equation of depinning fields from notches of ferromagnetic Permalloy nanowires is presented. The derived equation is given in the form of an explicit function of nanowire width and thickness, and notch depth and angle. The equation agrees with all micromagnetic simulation results to an accuracy of ${\pm}$ 0.5 mT.

• Transactions on Electrical and Electronic Materials
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• 제13권2호
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• pp.73-77
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• 2012

Operation of liquid crystal displays (LCDs) can be improved by monolithic integration of the pixel transistors with light emitting diodes (LEDs) on a single substrate. Conventional LCDs make use of filters to control the backlighting which reduces the overall efficiency. These LCDs also utilize LEDs in series which impose failure and they require high voltage for operation with a power factor correction. The screen of small hand-held devices can operate from moderate brightness. Therefore, III-V nanowires that are grown along with transistors over Silicon substrates can be utilized. Control of nanowire LEDs with nanowire transistors will significantly lower the cost, increase the efficiency, improve the manufacturing yield and simplify the structure of the small displays that are used in portable devices. The steps to grow nanowires on Silicon substrates are described. The vertical n-type and p-type nanowire transistors with surrounding gate structures are characterized. While biased at 0.5 V, nanowire transistors with minimum radius or channel width have an OFF current which is less than 1pA, an ON current more than 1 ${\mu}A$, a total delay less than 10 ps and a transconductance gain of more than 10 ${\mu}A/V$. The low power and fast switching characteristics of the nanowire transistor make them an ideal choice for the realization of future displays of portable devices with long battery lifetime.

• Journal of Electrical Engineering and Technology
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• 제9권6호
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• pp.2079-2088
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• 2014

In this paper, we propose new physically based threshold voltage models for short channel Surrounding Gate Silicon Nanowire Transistor with two different geometries. The model explores the impact of various device parameters like silicon film thickness, film height, film width, gate oxide thickness, and drain bias on the threshold voltage behavior of a cylindrical surrounding gate and rectangular surrounding gate nanowire MOSFET. Threshold voltage roll-off and DIBL characteristics of these devices are also studied. Proposed models are clearly validated by comparing the simulations with the TCAD simulation for a wide range of device geometries.

• Journal of Electrical Engineering and Technology
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• 제7권3호
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• pp.396-400
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• 2012

Novel fabrication method of nanobridge array of various materials was proposed using suspended silicon nanowire array as a sacrificial template structure. Nanobridges of various materials can be simply fabricated by direct deposition with thermal evaporation on the top of prefabricated suspended silicon nanobridge arrays, which are used as a sacrificial structure. Since silicon nanowire can be easily removed by selective dry etching, nanobridge arrays of an intended material are finally obtained. In this paper, metal nanobridges of Ti/Au, around 50-200 nm in thickness and width, 5-20 ${\mu}m$ in length were fabricated to prove the advantages of the proposed nanowire or nanobridge fabrication method. The nanobridges of Ti/Au after complete removal of sacrificial silicon nanowire template were well-established and bending of nanobridge caused by the tensile stress was observed after silicon removing. Up to 50 nm and 10 ${\mu}m$ of silicon nanowire in diameter and length respectively was also very useful for nanowire templates.

• Journal of Magnetics
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• 제13권4호
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• pp.167-169
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• 2008

The switching field of a 300 nm wide nanowire has been controlled by attaching a wide wire to it. The width of the wide wires varies from 700 nm to 2000 nm. While the connection of the two wires does not affect the switching field of the wide wires, it strongly affects the 300 nm-wire, resulting in a decrease of the switching field of the isolated wire from 175 Oe to 54 Oe when the 2000 nm-wire is connected to it. This result clearly shows that the switching field of the nanowire can be engineered by attaching a nucleation pad that has a different magnetic anisotropy.

• Journal of the Optical Society of Korea
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• 제12권2호
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• pp.65-68
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• 2008

The miniband structure of a quantum dot lattice based on GaN/AlN nanowire arrays has been investigated using the finite element method and Floquet theorem. The quantum dot modes and the quantum wire modes in the nanowire arrays were graphically verified. The optimum geometries of GaN/AlN quantum wire arrays were investigated by using a correlation between the width of nanowires and the separation of the minibandgap which is to be larger than the thermal energy at room temperature.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2015년도 추계학술대회
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• pp.879-882
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• 2015

본 연구에서는 시뮬레이션을 통해 채널 폭과 채널 도핑 형태에 따른 수직형 나노와이어 GAA MOSFET의 특성을 비교, 분석하였다. 첫 번째로, 드레인의 끝부분을 20nm로 고정시키고 소스의 끝부분이 30nm, 50nm, 80nm, 110nm로 식각된 모양으로 설계한 구조의 특성을 비교, 분석하였다. 두 번째로는 드레인, 채널, 소스의 폭이 50nm로 일정한 직사각형 모양의 구조를 설계하였다. 이 구조를 기준으로 삼아 드레인의 끝부분이 20nm가 되도록 식각된 사다리꼴 모양과 반대로 소스의 끝부분이 20nm가 되도록 식각된 역 사다리꼴 모양의 구조를 설계하여 위 세 구조의 특성을 비교, 분석하였다. 마지막으로는 폭 50nm의 직사각형 구조의 채널을 다섯 구간으로 나누어 도핑 형태를 다양하게 변화시킨 것의 특성을 비교, 분석하였다. 첫 번째 시뮬레이션에서는 채널 폭이 가장 작을 때, 두 번째 시뮬레이션에서는 사다리꼴 모양의 구조일 때, 세 번째 시뮬레이션에서는 채널의 중앙 부분이 높게 도핑 되었을 때 가장 좋은 특성을 보였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 춘계학술대회 논문집
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• pp.77-78
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• 2009

We report numerical simulations to investigate of the dependence of the on/off current ratio and channel charge distributions in silicon nanowire (SiNW) field-effect transistors (FETs) on the channel width and thicknesses. In order to investigate the transport behavior in devices with different channel geometries, we have performed detailed two-dimensional simulations of SiNWFETs and control FETs with a fixed channel length L of 10um, but varying the channel width W from 5nm to 5um, and thickness t from 10nm to 30nm. We have shown that $Q_{ON}/Q_{OFF}$ drastically decreases (from ${\sim}2.9{\times}10^4$ to ${\sim}9.8{\times}10^3$) as the channel thickness increases (from 10nm to 30nm). As a result of the simulation using a quantum model, even higher charge density in the bottom of SiNW channel was observed than that in the bottom of control channel.

• 한국정밀공학회지
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• 제29권3호
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• pp.334-338
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• 2012

Electrical isolation of Ag nanowire, which is one of the candidates as electrode for display devices, on polymer with femtosecond pulse laser has been investigated. Line patterning to Ag nanowire with various pulse energy and scan speed were experimented. Duo to the results of the line patterning experiment, we fabricated the isolated squares and measured electrical resistance. The profile of the selectively ablated area was analyzed with AFM(Atomic Force Microscope). The width of the patterned line was $1.8\;{\mu}m$ and the depth was $1.6\;{\mu}m$. We demonstrated electrical isolation of the Ag nanowire using femtosecond laser by evaluating the electrical resistance of the sample between isolated and opened area.