• Transactions on Electrical and Electronic Materials
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• v.14 no.3
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• pp.160-163
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• 2013

We investigated the effect of light intensity and wavelength of a solar cell device by using photoconductive atomic force microscopy (PC-AFM). The $POCl_3$ diffusion doping process was used to produce a p-n junction solar cell device based on a Poly-Si wafer and the electrical properties of prepared solar cells were measured using a solar cell simulator system. The measured open circuit voltage ($V_{oc}$) is 0.59 V and the short circuit current ($I_{sc}$) is 48.5 mA. Also, the values of the fill factors and efficiencies of the devices are 0.7% and approximately 13.6%, respectively. In addition, PC-AFM, a recent notable method for nano-scale characterization of photovoltaic elements, was used for direct measurements of photoelectric characteristics in local instead of large areas. The effects of changes in the intensity and wavelength of light shining on the element on the photoelectric characteristics were observed. Results obtained through PC-AFM were compared with the electric/optical characteristics data obtained through a solar simulator. The voltage ($V_{PC-AFM}$) at which the current was 0 A in the I-V characteristic curves increased sharply up to 1.8 $mW/cm^2$, peaking and slowly falling as light intensity increased. Here, $V_{PC-AFM}$ at 1.8 $mW/cm^2$ was 0.29 V, which corresponds to 59% of the average $V_{oc}$ value, as measured with the solar simulator. Also, while light wavelength was increased from 300 nm to 1,100 nm, the external quantum efficiency (EQE) and results from PC-AFM showed similar trends at the macro scale, but returned different results in several sections, indicating the need for detailed analysis and improvement in the future.

• Korean Journal of Materials Research
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• v.28 no.11
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• pp.680-684
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• 2018

We investigate the effect of light intensity and wavelength of a solar cell device using photoconductive atomic force microscopy(PC-AFM). A $POCl_3$ diffusion doping process is used to produce a p-n junction solar cell device based on a polySi wafer, and the electrical properties of prepared solar cells are measured using a solar cell simulator system. The measured open circuit voltage($V_{oc}$) is 0.59 V and the short circuit current($I_{sc}$) is 48.5 mA. Moreover, the values of the fill factors and efficiencies of the devices are 0.7 and approximately 13.6 %, respectively. In addition, PC-AFM, a recent notable method for nano-scale characterization of photovoltaic elements, is used for direct measurements of photoelectric characteristics in limited areas instead of large areas. The effects of changes in the intensity and wavelength of light shining on the element on the photoelectric characteristics are observed. Results obtained through PC-AFM are compared with the electric/optical characteristics data obtained through a solar simulator. The voltage($V_{PC-AFM}$) at which the current is 0 A in the I-V characteristic curves increases sharply up to $18W/m^2$, peaking and slowly falling as light intensity increases. Here, $V_{PC-AFM}$ at $18W/m^2$ is 0.29 V, which corresponds to 59 % of the average $V_{oc}$ value, as measured with the solar simulator. Furthermore, while the light wavelength increases from 300 nm to 1,100 nm, the external quantum efficiency(EQE) and results from PC-AFM show similar trends at the macro scale but reveal different results in several sections, indicating the need for detailed analysis and improvement in the future.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.499-499
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• 2011

Silicon nanowires (Si NWs) have been extensively studied for nanoelectronics owing to their unique optical and electrical properties different from those of bulk silicon. For the development of Si NW devices, better understanding of oxidation behavior in Si NWs would be an important issue. For example, it is widely known that atomic scale roughness at the dielectric (SiOx)/channel (Si) interface can significantly affect the device performance in the nano-scale devices. However, the oxidation process at the atomic-scale is still unknown because of its complexity. In the present work, we investigated the oxidation behavior of Si NW in atomic scale by simulating the dry oxidation process using a reactive molecular dynamics simulation technique. We focused on the residual stress evolution during oxidation to understand the stress effect on oxidation behavior of Si NWs having two different diameters, 5 nm and 10 nm. We calculated the charge distribution according to the oxidation time for 5 and 10 nm Si NWs. Judging from this data, it was observed that the surface oxide layer started to form before it is fully oxidized, i.e., the active diffusion of oxygen in the surface oxide layer. However, it is well-known that the oxide layer formation on the Si NWs results in a compressive stress on the surface which may retard the oxygen diffusion. We focused on the stress evolution of Si NWs during the oxidation process. Since the surface oxidation results in the volume expansion of the outer shell, it shows a compressive stress along the oxide layer. Interestingly, the stress for the 10 nm Si NW exhibits larger compressive stress than that of 5 nm Si NW. The difference of stress level between 5 an 10 anm Si NWs is approximately 1 or 2 GPa. Consequently, the diameter of Si NWs could be a significant factor to determine the self-limiting oxidation behavior of Si NWs when the diameter was very small.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.57-63
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• 2008

In this paper, the dependence of MOSFET performance on the channel stress is characterized in depth. The tensile and compressive stresses are applied to CMOSFET using a nitride film which is used for the contact etch stop layer (CESL). Drain current of NMOS and PMOS is increased by inducing tensile and compressive stress, respectively, due to the increased mobility as well known. In case of NMOS with tensile stress, both decrease of the back scattering ratio ($\tau_{sat}$) and increase of the thermal injection velocity ($V_{inj}$) contribute the increase of mobility. It is also shown that the decrease of the $\tau_{sat}$ is due to the decrease of the mean free path ($\lambda_O$). On the other hand, the mobility improvement of PMOS with compressive stress is analyzed to be only due to the so increased $V_{inj}$ because the back scattering ratio is increased by the compressive stress. Therefore it was confirmed that the device performance has a strong dependency on the channel back scattering of the inversion layer and thermal injection velocity at the source side and NMOS and PMOS have different dependency on them.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.23-28
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• 2010

In this paper, comparative analysis of digital and analog performances of strained-silicon PMOSFETs with different carrier direction were performed. ID.SAT vs. ID.OFF and output resistance, Rout performances of devices with <100> carrier direction were better than those of <110> direction due to the greater carrier mobility of <100> channel direction. However, on the contrary, NBTI reliability and device matching characteristics of device with <100> carrier direction were worse than those with <110> carrier direction. Therefore, simultaneous consideration of analog and reliability characteristics as well as DC device performance is highly necessary when developing mobility enhancement technology using the different carrier direction for nano-scale CMOSFETs.

• Journal of the Korean Society for Precision Engineering
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• v.27 no.1
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• pp.125-133
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• 2010

A versatile micro-robotic platform for micro/nano scale assembly has been demanded in a variety of application areas such as micro-biology and nanotechnology. In the near future, a flexible and compact platform could be effectively used in a scanning electron microscope chamber. We are developing a platform that consists of miniature mobile robots and a compact positioning stage with multi degree-of-freedom. This paper presents the design and the implementation of a low-cost and compact multi degree of freedom position sensor that is capable of measuring absolute translational and rotational displacement. The proposed sensor is implemented by using a CMOS type image sensor and a target with specific hole patterns. Experimental design based on statistics was applied to finding optimal design of the target. Efficient algorithms for image processing and absolute position decoding are discussed. Simple calibration to eliminate the influence of inaccuracy of the fabricated target on the measuring performance also presented. The developed sensor was characterized by using a laser interferometer. It can be concluded that the sensor system has submicron resolution and accuracy of ${\pm}4{\mu}m$ over full travel range. The proposed vision-based sensor is cost-effective and used as a compact feedback device for implementation of a micro robotic platform.

• Journal of the Korean Society for Geothermal and Hydrothermal Energy
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• v.17 no.1
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• pp.14-22
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• 2021

Drilling equipment is an essential part used in various fields such as construction, mining, etc., and it has drawn increasing attention in recent years. The drilling method is generally divided into three types. There are a top hammer method that strikes on the ground, a DTH (Down-The-Hole) method that directly strikes a bit in an underground area, and a rotary method that drills by using rotational force. Among them, the DTH method is most commonly used because it enables efficient drilling compared to other drilling methods. In the conventional DTH hammer, the valve between the piston and the bit is opened and closed using a face to face method. In order to improve the power of the DTH hammer, a DTH hammer with foot valve which is capable of instantaneous opening and closing is used in the drilling field. In this study, we designed a lab-scale DTH hammer with the foot valve, and manufactured an evaluation device for the experiment of the DTH hammer. In addition, we analyzed the performance of the DTH hammer adopted with foot valve according to the pressure range of 3-10 bar. As a result, the internal pressure distribution in the DTH hammer was experimentally analyzed, and then, the movement of the piston according to the pressure was predicted. We believe that this study provides the useful results to explain the performance characteristics of the DTH hammer with the foot valve.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.365-368
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• 2002

We investigated the influence of RTP annealing of multi-layered metal films deposited on oxides layer. Two types of oxides, BPSG and P-7205, were used as a bottom layer under multi-layered metal film. The bonding was not good in metal/BPSG/Si samples because adhesion between metal layer and BPSG oxide layer was poor by interfacial reaction during RTP annealing above 650$^{\circ}C$. On the other hand bonding was always good in metal/ P-TEOS /Si samples regardless of annealing temperature. We observed the interface between oxide and metal layers using AES and TEM. The phosphorus and oxygen profile in interface between metal and oxide layers were different in metal/BPSG/Si and metal/P-TEOS/Si samples. We have known that the properties of interface was improved in metal/BPSG/Si samples when the sample was annealed below 650$^{\circ}C$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.4
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• pp.719-724
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• 2003

In this paper, we have presented the simulation results about threshold voltage of nano scale lightly doped drain (LDD) MOSFET with halo doping profile. Device size is scaled down from 100nm to 40nm using generalized scaling. We have investigated the threshold voltage for constant field scaling and constant voltage scaling using the Van Dort Quantum Correction Model (QM) and direct tunneling current for each gate oxide thickness. We know that threshold voltage is decreasing in the constant field scaling and increasing in the constant voltage scaling when gate length is reducing, and direct tunneling current is increasing when gate oxide thickness is reducing. To minimize the roll off characteristics for threshold voltage of MOSFET with decreasing channel length, we know $\alpha$ value must be nearly 1 in the generalized scaling.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.133-134
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• 2006

A simple doping method to fabricate a very thin channel body of the n-type fin field-effect-transistor (FinFET) with a 20 nm gate length by solid-phase-diffusion (SPD) process is presented. Using As-doped spin-on-glass as a diffusion source of arsenic and the rapid thermal annealing, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. Single channel and multi-channel n-type FinFET devices with a gate length of 20-100 nm was fabricated by As-SPD and revealed superior device scalability.