• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.322-325
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• 2005

The shrinking critical dimensions of modern technology place a heavy requirement on optimizing feature shapes at the micro- and nano scale. In addition, the use of ion beams in the nano-scale world is greatly increased by technology development. Especially, Focused ion Beam (FIB) has a great potential to fabricate the device in nano-scale. Nevertheless, FIB has several limitations, surface swelling in low ion dose regime, precipitation of incident ions, and the re-deposition effect due to the sputtered atoms. In recent years, many approaches and research results show that the re-deposition effect is the most outstanding effect to overcome or reduce in fabrication of micro and nano devices. A 2D string based simulation software AMADEUS-2D $(\underline{A}dvanced\;\underline{M}odeling\;and\;\underline{D}esign\;\underline{E}nvironment\;for\;\underline{S}putter\;Processes)$ for ion milling and FIB direct fabrication has been developed. It is capable of simulating ion beam sputtering and re-deposition. In this paper, the 2D FIB simulation is demonstrated and the characteristics of ion beam induced direct fabrication is analyzed according to various parameters. Several examples, single pixel, multi scan box region, and re-deposited sidewall formation, are given.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.18 no.4
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• pp.369-374
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• 2009

In micro/nano-scale contacts in MEMS and NEMS, capillary and van der Waals forces generated around contacting micro-asperities significantly influence the performance of concerning device as they are closely related to adhesion and stiction of interacting surfaces. In this regard, it is of prime importance to accurately estimate the magnitude of surface forces so that an optimal solution for reducing friction and adhesion of micro/nano-surfaces may be obtained We introduced an effective method to calculate these surface forces based on topography information obtained from an atomic force microscope. This method was used to calculate surface forces generated in the contact interface formed between diamond-like carbon coating and $Si_3N_4$ ball. This method is shown to effectively demonstrate the influence of capillary force in the contact area, especially in humid atmosphere.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2008.05a
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• pp.513-516
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• 2008

We have replicated nanopillar arrays using injection molding process of active heating and cooling method by several peltier devices. The injection melding has a high accuracy ed good reproducibility that are essential for mass production at low cost. Conventional molding processes widely use the water-based mold heating and air cooling methods. However, in case of replication for nano-patterned structures, it caused several defects such as air-flow mark, non-fill, sticking and tearing. In this study, periodic nano-scale patterns are replicated by using injection molding with Peltier devices. Porous nano-scale patterns, which have pore diameter range from 120nm to 150nm, were fabricated by using anodizing process. Periodic nano-pore structures ( $20mm\;{\times}\;20mm$) were used as a mold stamp of injection molding. Finally, PMMA with nanopillar arrays was obtained by injection molding process. By using the Peltier devices, the temperature of locally adiabatic molds can be dramatically controlled and the quality of the molded patterns can be slightly improved.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.57-57
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• 2010

In this study, nano-sized phase change materials were evaluated using nanoimprint lithography and c-AFM technique. The 200nm in diameter phase change nano-pillar device of GeSbTe, AgInSbTe, InSe, GeTe, GeSb were successfully fabricated using nanoimprint lithography. And the electrical properties of the phase change nano-pillar device were evaluated using c-AFM with pulse generator and voltage source.

• KIEE International Transactions on Electrophysics and Applications
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• v.5C no.2
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• pp.49-53
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• 2005

The current drive in a MOSFET is limited by the intrinsic channel resistance. All other parasitic elements in a device structure perform significant functions leading to degradation in the device performance. These other resistances must be less than 10$\%$-20$\%$ of the channel resistance. To meet the necessary requirements, the methodology of separation and quantification of those resistances should be investigated. In this paper, we developed an extraction method for the resistances using calibrated TCAD simulation. The resistance of the extension region is also partially determined by the formation of a surface accumulation region that gathers below the gate in the tail region of the extension profile. This resistance is strongly affected by the abruptness of the extension profile because the steeper the profile is, the shorter this accumulation region will be.

• Journal of the Korean Society for Precision Engineering
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• v.31 no.12
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• pp.1067-1076
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• 2014

To date, biomedical application of three-dimensional (3D) printing technology remains one of the most important research topics and business targets. A wide range of approaches have been attempted using various 3D printing systems with general materials and specific biomaterials. In this review, we provide a brief overview of the biomedical applications using 3D printing techniques, such as surgical tool, medical device, prosthesis, and tissue engineering scaffold. Compared to the other applications of 3D printed products, the scaffold fabrication should be performed with careful selection of bio-functional materials. In particular, we describe how the biomaterials can be processed into 3D printed scaffold and applied to tissue engineering area.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.12
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• pp.1017-1021
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• 2007

To implement tera bit level non-volatile memories of low power and fast operation, proving statistical reproductivity and satisfying reliabilities at the nano-scale are a key challenge. We fabricate the charge trapping nano scaled SONOS unit memories and 64 bit flash arrays and evaluate reliability and performance of them. In case of the dielectric stack thickness of 4.5 /9.3 /6.5 nm with the channel width and length of 34 nm and 31nm respectively, the device has about 3.5 V threshold voltage shift with write voltage of $10\;{\mu}s$, 15 V and erase voltage of 10 ms, -15 V. And retention and endurance characteristics are above 10 years and $10^5$ cycle, respectively. The device with LDD(Lightly Doped Drain) process shows reduction of short channel effect and GIDL(Gate Induced Drain Leakage) current. Moreover we investigate three different types of flash memory arrays.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.1-7
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• 2004

We performed two-dimensional (20) computer-based modeling and simulation of FinFET by solving the coupled Poisson-Schrodinger equations quantum-mechanically in a self-consistent manner. The simulation results are carefully investigated for FinFET with gate length(Lg) varying from 10 to 80nm and with a Si-fin thickness($T_{fin}$) varying from 10 to 40nm. Current-voltage (I-V) characteristics are compared with the experimental data. Device optimization has been performed in order to suppress the short-channel effects (SCEs) including the sub-threshold swing, threshold voltage roll-off, drain induced barrier lowering (DIBL). The quantum-mechanical simulation is compared with the classical appmach in order to understand the influence of the electron confinement effect. Simulation results indicated that the FinFET is a promising structure to suppress the SCEs and the quantum-mechanical simulation is essential for applying nano-scale device structure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.1-8
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• 2006

In this paper, reliability (HCI, NBTI) and device performance of nano-scale CMOSFETs with different channel stress were investigated. It was shown that NMOS and PMOS performances were improved by tensile and compressive stress, respectively, as well known. It is shown that improved device performance is attributed to the increased mobility of electrons or holes in the channel region. However, reliability characteristics showed different dependence on the channel stress. Both of NMOS and PMOS showed improved hot carrier lifetime for compressive channel stress. NBTI of PMOS also showed improvement for compressive stress. It is shown that $N_{it}$ generation at the interface of $Si/SiO_2$ has a great effect on the reliability. It is also shown that generation of positive fixed charge has an effect in the NBTI. Therefore, reliability as well as device performance should be considered in developing strained-silicon MOSFET.

• Proceedings of the Materials Research Society of Korea Conference
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• 2010.05a
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• pp.30.2-30.2
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• 2010

Nano-scale p-n junction can generate various nano-scale functional devices such as nanowire light emitting diode, nanowire solar cell, and nanowire sensor. The core shell type nanowire p-n junction has been considered for the high efficient devices in many previous reports. On the other hand, although device efficiency is relatively lower, the cross bar type p-n junction has simple topological structure, suggested by C.M. Lieber group, to integrate easily many p-n junction devices in one board. In this study, for the integration of the cross bar nanowire p-n junction device, a simple fabrication route, employed dielectrophoretic array and direct printing techniques, was demonstrated by the successful fabrication and programmable integration of the nanowire cross bar p-n junction solar cell. This direct printing process will give the single nanowire solar cell the opportunity of the integration on the circuit board with other nanowire functional devices.