• Journal of the Microelectronics and Packaging Society
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• v.23 no.3
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• pp.1-6
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• 2016

The Internet of Things (IoT) is a new technology paradigm demanding one packaged system of various semiconductor and MEMS devices. Therefore, the development of electronic packaging technology with very high connectivity is essential for successful IoT applications. This paper discusses both fan-out wafer level packaging (FOWLP) and 3D stacking technologies to achieve the integrattion of heterogeneous devices for IoT. FOWLP has great advantages of high I/O density, high integration, and design flexibility, but ultra-fine pitch redistribution layer (RDL) and molding processes still remain as main challenges to resolve. 3D stacking is an emerging technology solving conventional packaging limits such as size, performance, cost, and scalability. Among various 3D stacking sequences wafer level via after bonding method will provide the highest connectivity with low cost. In addition substrates with ultra-thin thickness, ultra-fine pitch line/space, and low cost are required to improve system performance. The key substrate technologies are embedded trace, passive, and active substrates or ultra-thin coreless substrates.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.4
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• pp.29-32
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• 2009

Dense and periodic arrays of nano-sized holes were patterned in oxide thin film on GaAs substrate. To obtain the nano-size patterns, self-assembling diblock copolymer was used to produce thin film of uniformly distributed parallel cylinders of polymethylmethacrylate (PMMA) in polystyrene (PS) matrix. The PMMA cylinders were removed with UV expose and acetic acid rinse to produce PS nanotemplate. By reactive ion etching, pattern of the PS template was transferred to under laid silicon oxide layer. Transferred patterns were reached to the GaAs substrate by controlling the dry etching time. We confirmed the achievement of etching through the removing oxide layer and observation of GaAs substrate surface. Optimized etching time was 90 to 100 sec. Pore sizes of the nanopattern in the silicon oxide layer were 20~22 nm.

• Journal of the Korea Organic Resources Recycling Association
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• v.32 no.3
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• pp.57-66
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• 2024

In this study, silicon sludge from a semiconductor packaging process is recycled to fabricate silica coated silicon-sludge and applied as a filler for an epoxy molding compound(EMC). Silicon-sludge powder(S-sludge) is treated with acid to remove metallic impurities and then coated using the sol-gel method to synthesize silica coated silicon-sludge powder(SS-sludge). The as-synthesized SS-sludge is subsequently mixed with epoxy resin, a curing agent, and carbon black to create an EMC(SS-sludge EMC). The heat dissipation properties of the EMC were examined using an IR camera. IR camera analysis confirmed that the SS-sludge EMC exhibited the highest surface temperature of 58.5℃ compared to SiO₂-based EMC. This enhancement in heat dissipation using SS-sludge EMC is attributed to the excellent thermal conductivity(150W/mK) of the silicon substrate and the presence of the silica layer on the SS-sludge surface which effectively enhances the thermal property of the EMC. Therefore, this study successfully demonstrates the recycling of silicon sludge from a semiconductor packaging process by synthesizing silica coated silicon-sludge and suggests a novel application of this material in semiconductor packaging.

• Korean Journal of Materials Research
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• v.17 no.7
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• pp.347-351
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• 2007

Vertical interconnect technology called 3D stacking has been a major focus of the next generation of IC industries. 3D stacked devices in the vertical dimension give several important advantages over conventional two-dimensional scaling. The most eminent advantage is its performance improvement. Vertical device stacking enhances a performance such as inter-die bandwidth improvements, RC delay mitigation and geometrical routing and placement advantages. At present memory stacking options are of great interest to many industries and research institutes. However, these options are more focused on a form factor reduction rather than the high performance improvements. In order to improve a stacked device performance significantly vertical interconnect technology with wafer level stacking needs to be much more progressed with reduction in inter-wafer pitch and increases in the number of stacked layers. Even though 3D wafer level stacking technology offers many opportunities both in the short term and long term, the full performance benefits of 3D wafer level stacking require technological developments beyond simply the wafer stacking technology itself.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.180-182
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• 2002

Copper thin films are prepared by a chemical vapor deposition technology for multi-level metallzations in ULSI fabrication. The copper films were deposited on TiN/Si substrates in helium atmosphere with the substrate temperature between $120^{\circ}C$ and $300^{\circ}C$. In order to get more reliable metallizations, effects on the post-annealing treatment to the electrical properties of the copper films have been investigated. The Cu films were annealed at the $5\times$10^{-6}$ Torr vacuum condition, and the electrical resistivity and the nano-structures were measured for the Cu films. The electrical resistivity of Cu films shown to be reduced by the post-annealing. The electrical resistivity of 2.2 $\mu$$\Omega$.cm was obtained for the sample deposited at the substrate temperature of $180^{\circ}C$ after vacuum annealed at $300^{\circ}C$. The resistivity variations of the films was not exactly matched with the size of the nato-structures of the copper grains, but more depended on the deposition temperature of the copper films.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.92-97
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• 2002

We establish a visible light emission from porous polycrystalline silicon nano structure(PPNS). The PPNS layer are formed on heavily doped n-type Si substrate. 2um thickness of undoped polycrystalline silicon deposited using LPCVD (Low Pressure Chemical Vapor Deposition) anodized in a HF: ethanol(=1:1) as functions of anodizing conditions. And then a PPNS layer thermally oxidized for 1 hr at $900 ^{\circ}C$. Subsequently, thin metal Au as a top electrode deposited onto the PPNS surface by E-beam evaporator and, in order to establish ohmic contact, an thermally evaporated Al was deposited on the back side of a Si-substrate. When the top electrode biased at +6V, the electron emission observed in a PPNS which caused by field-induces electron emission through the top metal. Among the PPNSs as functions of anodization conditions, the PPNS anodized at a current density of $10mA/cm^2$ for 20 sec has a lower turn-on voltage and a higher emission current. Furthermore, the behavior of electron emission is uniformly maintained.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.98-103
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• 2002

BGA(Ball Grid Array) 패키지의 솔더볼 패드 중의 하나인 Au/Ni-Co/Cu 금속층 위에 Bi가 첨가된 Sn-3.5Ag-$\chi$Bi 솔더볼을 리플로우시켰다. 리플로우한 후 130 $^{\circ}C$에서 열처리함에 따른 계면상 및 솔더 내부의 상변화를 관찰하였다. 계면에는 (Ni,Co)$_3$Sn$_4$외에 (Au,Ni,Co,Bi)Sn$_4$가 생성되었음을 관찰할 수 있었고, 솔더 내부에는 (Au,Ni,Co,Bi)SH$_4$, Ag$_3$Sn, Bi 상이 혼재되어 있었다. Nano-indentation에 의한 경도 측정 결과, Bi 함량 증가에 따라 경도는 증가하였으나, 볼전단(Ball Shear) 테스트 결과는 Bi가 증가됨에 따라 오히려 볼전단 강도값이 감소하였다. 이는 파면 검사 결과, 파괴 경로가 주로 계면의 금속간 화합물과 솔더 사이에서 진행함에 기인한 것이다. 솔더 내부의 파괴 경로를 가진 2.5Bi가 가장 우수한 볼전단 강도값을 나타내었는데, 이는 솔더내의 Bi의 고용강화에 기인한 것으로 보인다.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.97-99
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• 2002

유리내부에 수십나노크기의 Ag 금속입자를 생성시키기 위한 연구를 진행하였다. 본 연구에서는 규산염계 유리에 Ag와 Ce을 첨가하여 환원분위기에서 유리를 제조함으로서 Ce$^{3+}$ 를 유리내에 생성시킬 수 있었으며, 또한 레이저조사(irradiation)를 통하여 Ag+이온의 금속입자 환원을 도울 수 있었다. 또한 레이저 조사시간에 따른 금속입자의 변화를 관찰하고자 하였으며, 이와 같은 과정으로 생성된 금속입자함유 유리를 열처리함으로서 나타나는 열적특성을 평가하여 금속입자가 결정화과정에 미치는 영향을 평가하고자 하였다. 유리내에 존재하는 나노금속입자를 투과전자현미경 (TEM)을 통하여 확인하였으며, 시차주사열량분석법(DSC)을 통해 유리의 결정화거동을 평가하였다. 또한 Photo Luminescence 측정을 통한 유리내부의 Ce이온의 전자상태를 관찰하였다.

• Journal of the Semiconductor & Display Technology
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• v.16 no.2
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• pp.19-26
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• 2017

The cure properties of ethoxysilyl bisphenol A type epoxy resin (Ethoxysilyl-DGEBA) systems with different hardeners were investigated, comparing with DGEBA and Diallyl-DGEBA epoxy resin systems. The cure kinetics of these systems were analyzed by differential scanning calorimetry with an isothermal approach, and the kinetic parameters of all systems were reported in generalized kinetic equations with diffusion effects. The Ethoxysilyl-DGEBA epoxy resin system showed lower cure conversion rates than DGEBA and Diallyl-DGEBA epoxy resin systems. The conversion rates of these epoxy resin systems with DDM hardener are lower than those with HF-1M hardener. It can be considered that the optimum hardener for Ethoxysilyl-DGEBA epoxy resin system is Phenol Novolac type. These lower cure conversion rates in the Ethoxysilyl-DGEBA epoxy resin systems could be explained by the retardation of reaction molecule movements according to the formation of organic-inorganic hybrid network structure by epoxy and ethoxysilyl group in Ethoxysilyl- DGEBA epoxy resin system.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.1
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• pp.17-24
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• 2020

As an interconnect scaling faces a technical bottleneck, the device stacking technologies have been developed for miniaturization, low cost and high performance. To manufacture a stacked device structure, a vertical interconnect becomes a key process to enable signal and power integrities. Most bonding materials used in stacked structures are currently solder or Cu pillar with Sn cap, but copper is emerging as the most important bonding material due to fine-pitch patternability and high electrical performance. Copper bonding has advantages such as CMOS compatible process, high electrical and thermal conductivities, and excellent mechanical integrity, but it has major disadvantages of high bonding temperature, quick oxidation, and planarization requirement. There are many copper bonding processes such as dielectric bonding, copper direct bonding, copper-oxide hybrid bonding, copper-polymer hybrid bonding, etc.. As copper bonding evolves, copper-oxide hybrid bonding is considered as the most promising bonding process for vertically stacked device structure. This paper reviews current research trends of copper bonding focusing on the key process of Cu-SiO₂ hybrid bonding.