• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.692-696
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• 1997

본 연구에서는 BJT(Bipolar Junction Transistor)와 MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 등을 1MeV에너지의 전자빔을 선량을 변화시켜가며 조사시켜 그 특성 변화를 분석하였다. BJT에 대해서는 조사 전, 후의 전류 이득의 측정을 통해 base 에서의 minority-carrie의 수명 변화에 의해서 전류 이득이 감소하는 것으로 나타났으며, MOSFET의 경우는 oxide 지역의 전하량 변화에 의해서 문턱 전압이 영향을 받음을 확인할 수 있었다. BJT의 minority-carrier의 수명 감소량은 조사 선량이 증가함에 따라 직선적으로 변화함을 알 수 있었고, MOSFET의 문턱 전압의 변화는 nMOS와 pMOS의 경우 서로 다름을 관찰할 수 있었는데 이는 oxide내에서 발생하는 전하에 의해 차이가 남을 알 수 있었다.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.1
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• pp.17-22
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• 2001

The floating-gate MOSFETs were fabricated by employing 1.5 m n-well CMOS process and their optical-electrical properties were characterized for the application to CMOS image sensor system. Based on the simulation of energy band diagram and operating mechanism of parasitic BJT were proposed as solutions for the increase of photo-current value. In order to realize them, MOSFETs having multi-gate and channel structures were fabricated and 60% increase in photo-current was achieved through enlargement of depletion layer and parallel connection of parasitic BJTs by channel division.

• Proceeding of EDISON Challenge
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• 2017.03a
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• pp.428-432
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• 2017

Silicon 기반 Metal-oxide-semiconductor field-effect transistor (MOSFET)의 크기가 감소함에 따라 silicon자체의 물성적 한계가 나타나고 있다. 이를 극복하고자 III-V 화합물 반도체가 채널소자로서 각광받고 있다. 본 연구에서는 III-V 화합물반도체 중 $In_xGa_{1-x}As$는 Indium 조성에 따른 전자구조 및 n-type MOSFET의 소자 특성을 본다. Indium의 조성이 증가함에 따라 subband의 개수와 간격이 증가하게 되어 Density of state가 감소하게 된다. 이로 인하여 Indium의 조성이 증가함에 따라 $In_xGa_{1-x}As$ 채널 MOSFET에서 상대적으로 Fermi level을 더 많이 상승시키게 되어 potential barrier를 얇아지게 만들며 또한 에너지에 따른 전류 밀도를 넓게 분포하도록 만든다. 이로 인하여 단채널에서는 In 조성이 증가함에 따라 direct source-to-drain tunnelling current이 증가하게 된다. 이로 인하여 In 조성의 증가에 따라 subthreshold swing과 ON-state current가 저하된다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.5
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• pp.818-822
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• 1987

Gate capacitances have been measured directly on small-geometry MOSFET's with the drain voltage as a parameter for various channel lengths and for p and n channel types and the characteristics have been compared with each other. The influence of 'hot carrier effect' of short channel devices on capaciatance has been compared with long channel devices. The results show that gate capacitance characteristics of short channel device deviate from those of long channel device. The accuracy of the measurement system is less than a few femto Farad, and the minimum geometry (W/L) of device for which reliable measurement can be obtained is 6/3.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.8
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• pp.34-45
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• 1994

We studied threshold voltages and I-V characteristics. considering short channel effect of the fully depleted thin film n-channel SOI MOSFET. We presented a charge sharing model when the back surface of short channel shows accumulation depletion and inversion state respectively. A degree of charge sharing can be compared according to each of back-surface conditions. Mobility is not assumed as constant and besides bulk mobility both the mobility defined by acoustic phonon scattering and the mobility by surface roughness scattering are taken into consideration. I-V characteristics is then implemented by the mobility including vertical and parallel electric field. kThe validity of the model is proved with the 2-dimensional device simulation (MEDICI) and experimental results. The threshold voltage and charge sharing region controlled by source or drain reduced with increasing back gate voltage. The mobility is dependent upon scattering effect and electric field. so it has a strong influence on I-V characteristics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.44-48
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• 1999

In order to the investigate for the DC(forward-reverse) breakdown properties of gate oxide in MOSFET, we are manufactured the specimen as following. The resistivity is 1.2($\Omega$ $.$ cm), 1.5($\Omega$ $.$ cm) and 1.8($\Omega$ $.$ cm) when thickness is 600(${\AA}$), and the diffusion time is both 110[min] and 150[min] when thickness is 600[${\AA}$]. In DC dielectric strength due to the each resistivity, it is confirmed that almost of the leakage current and breakdown current is flowed through n+ source when positive bias is applied, but is flowed through P region when negative bias is applied. It is thought that the dielectric strength due to the diffusion time is the contribution as increasing of p region.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.7
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• pp.584-592
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• 2003

6H-SiC MOSFETs and digital ICs have been fabricated and characterized. PMOS devices are fabricated on an n-type epilayer while the NMOS devices are fabricated on implanted p-wells. NMOS and PMOS devices use a thermally grown gate oxide. SiC MOSFETs are fabricated using different impurity activation methods such as high temperature and newly proposed laser annealing methods. Several digital circuits, such as resistive road NMOS inverters, CMOS inverters, resistive road NMOS NANDs and NORs are fabricated and characterized.

• Journal of Electrical Engineering and Technology
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• v.9 no.3
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• pp.964-969
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• 2014

In Super Junction MOSFET, Charge Balance is the most important issue of the trench filling Super Junction fabrication process. In order to achieve the best electrical characteristics, the N type and P type drift regions must be fully depleted when the drain bias approaches the breakdown voltage, called Charge Balance Condition. In this paper, two methods from the fabrication process were used at the Charge Balance condition: Trench angle decreasing process and Bottom implantation process. A lower on-resistance could be achieved using a lower trench angle. And a higher breakdown voltage could be achieved using the bottom implantation process. The electrical characteristics of manufactured discrete device chips are compared with those of the devices which are designed of TCAD simulation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.5
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• pp.347-352
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• 1998

In this paper, the extraction and optimization of SPICE parameters on SONOSFET for NVSM circuit design were discussed. SONOSFET devices with different channel widths and lengths were fabricated using conventional 1.2 um n-well CMOS process. And, electric properties for dc parameters and capacitance parameters were measured on wafer. SPICE parameters for the SONOSFET were extracted from the UC Berkeley level 3 model for the MOSFET. And, local optimization of Ids-Vgs curves has carried out in the bias region of subthreshold, linear, saturation respectively. Finally, the extracted SPICE parameters were optimized globally by comparing drain current (Ids), output conductance(gds), transconductance(gm) curves with theoretical curves in whole region of bias conditions. It is shown that the conventional model for the MOSFET can be applied to the SONOSFET modeling except sidewalk effect.

• Journal of the Korea Institute of Military Science and Technology
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• v.25 no.5
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• pp.545-551
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• 2022

We proposed a design method for constant current pyro squib circuit. The current method using N MOSFET for the stability problem has a weakness of the current change, requiring a new design. This paper identified the problem with conventional squib circuit where the current is reduced by 25 % when maximum resistance is 3 ohms. Thus, we proposed a stable constant current driving circuit using P MOSFET and PNP BJT. We confirmed stable constant circuit operation through simulations and measurements of the proposed circuit design where the current did not change until the resistance reached 3 ohms.