• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.291-294
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• 1998

The objective of this study is to deposited the preparation of STO dielectric thin films on Ag/barrier-mater/Si(N-type 100) bottom electrode using a conventional rf-magnetron sputtering technique with a ceramic target under various conditions. It is demonstrated that the leakage current of films are strongly dependent on the atmosphere during deposition and the substrate temperature. The resistivity properties of films deposited on silicon substrates were very high resistivity. Capacitance of the films properties were the highest value(1000pF) and dependent on substrate temperature.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.8
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• pp.34-41
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• 1993

Effect of high temperature annealing conditions on Ta$_{2}O_{5}$ thin films was investigated. Ta$_{2}O_{5}$ thin films were deposited on P-type silicon substrates by plasma-enhanced chemical vapor deposition (PECVD) using tantalum ethylate. Ta(C$_{2}H_{5}O)_{5}$, and nitrous oxide. N$_{2}$O. The microstructure changed from amorphous to polycrystalline above 700.deg. C annealing temperature. The refractive index, dielectric onstant and leakage current of the film increased as annealing temperature increased. However, annealing in oxygen ambient reduced leakage currents and dielectric constant due to the formation of interfacial SiO$_{2}$ layer. By optimizing annealing temperature and ambient, leakage current lower than 10$^{-8}$ A/cm$^{2}$ and maximum capacitance of 9 fF/${\mu}m^{2}$ could be obtained.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.156-161
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• 2017

This work presents a novel structure for junction-less tunneling field effect transistor (JL-TFET) with a floating gate over the source region. Introduction of floating gate instead of fixed metal gate removes the limitation of fabrication process suitability. The proposed device is based on a heavily n-type-doped Si-channel junction-less field effect transistor (JLFET). A floating gate over source region and a control-gate with optimized metal work-function over channel region is used to make device work like a tunnel field effect transistor (TFET). The proposed device has exhibited excellent ID-VGS characteristics, ION/IOFF ratio, a point subthreshold slope (SS), and average SS for optimized device parameters. Electron charge stored in floating gate, isolation oxide layer and body doping concentration are optimized. The proposed JL-TFET can be a promising candidate for switching performances.

• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1514-1515
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• 1998

Diamond thin films were deposited on n-type (100) Si wafers from $H_2-CH_4$ gas mixture by rf PACVD. Prior to deposition, mechanical scratching was done to improve density of nucleation sites with diamond paste of 3${\mu}m$. The microstructure of deposited diamond thin films was studied by using the following conditions : discharge power of 500W, $H_2$ flow rate of 50sccm, reaction pressure of 20torr, and $CH_4/H_2$ ratio of 0.3$\sim$1%. The deposited diamond thin films showed that the crystallite was increased at the lower methane concentration. The deposited thin films were characterized by Scanning Electron Microscopy. Raman Spectroscopy and Fourier-Transform Infrared Spectroscopy.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.4
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• pp.361-364
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• 2008

Tips of probe card were fabricated using MEMS technology. P-type silicon wafer with $SiO_2$ layer was used as a substrate for fabricating the probe card. Ni-Cr and Au used as seed layer for electroplating Ni were deposited on the silicon wafer. Line patterns for probing devices were formed on silicon wafer by electroplating Ni through mold which formed by MEMS technology. Bridge structure was formed by wet-etching the silicon substrate. AZ-1512 photoresist was used for protection layer of back side and DNB-H100PL-40 photoresist was used for patterning of the front side. The mold with the thickness of $60{\mu}m$ was also formed using THB-120N photoresist and probe tip with thickness of $50{\mu}m$ was fabricated by electroplating process.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.8
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• pp.56-62
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• 1992

This paper is analyzed the charge trapping and electrical properties of 0(Oxide), NO(Nitrided oxide) and ONO(Reoxidized nitrided oxide) as dielectric films in MIS structures. We have processed bottom oxide and top oxide by the thermal method, and nitride(Si$_{3}N_{4}$) by the LPCVD(Low Pressure Chemical Vapor Deposition) method on P-type(100) Silicon wafer. We have studied the charge trapping properties of the dielectrics by using a computer controlled DLTS system. All of the dielectric films are shown peak nearly at 300K. Those are bulk traps. Many trap densities which is detected in NO films, but traps. Many trap densities which is detected in NO films. Varing the nitride thickness, the trap densities of thinner nitride is decreased than the thicker nitride. Finally we have found that trap densities of ONO films is affected by nitride thickness.

• Molecular & Cellular Toxicology
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• v.2 no.4
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• pp.279-284
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• 2006

This paper describes the fabrication methods of a carbon nanotube (CNT) filter and a microdialysis chip. A CNT filter can help perform dialysis on a microfluidic chip. In this study, a membrane type of a CNT filter is fabricated and located in a microfluidic chip. The filter plays a role of a dialysis membrane in a microfluidic chip. In the fabrication process of a CNT filter, individual CNTs are entangled each other by amide bonding that is catalyzed by 1-Ethyl-3-(3-dimethylaminopropyl)carbodiimide (EDC) and N-hydroxysuccinimide (NHS). The chemically treated CNTs are shaped to form a CNT filter using a PDMS film-mold and vacuum filtering. Then, the CNT filter is sandwiched between PDMS substrates, and they are bonded together using a thin layer of PDMS prepolymer as adhesive. The PDMS substrates are fabricated to have a microchannel by standard photo-lithography technique.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.119-119
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• 2000

A new type of low voltage driven SrTiO3 varistor was investigated. $SrTi3_3$ sintered with CuO-SiO2 additions, the sintering temperature was reduced to 1250-1300C. With the sintering additives, the semiconducting SrTi03 was able to fabricate single time sintering in reducing atmosphere(95% N2 + 5% H2), The non-linear coefficient value was 10.3 and the operating voltage was about 7 V.

• Journal of the Korean Ceramic Society
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• v.47 no.4
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• pp.290-295
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• 2010

This study has been focused on properties of mirror surface grinding technology by ELID(Electrolytic In-process Dressing) for structural ceramics using in high precision structural parts as like semi-conductor manufacturing processes. The experimental studies have been carried out to get mirror surface for grinding of structural ceramics, SiC, $Al_2O_3$ and AlN. Grinding process of the ceramics is carried out with varying mesh type, depth of cut and feed rate using diamond wheel. The machining result of the surface roughness and condition of ground surface, have been analyzed by use of surface roughness tester, SEM, AFM and three dimensional surface profiler measurement system.

• Journal of information and communication convergence engineering
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• v.13 no.4
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• pp.257-263
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• 2015

In this study, organic field-effect transistors (OFETs) using a copper phthalocyanine (CuPc) material as an active layer and SiO₂ as a gate insulator were fabricated with varying active layer thicknesses and channel lengths. Further, using a thermal evaporation method in a high-vacuum system, we fabricated a CuPc FET device of the top-contact type and used Au materials for the source and drain electrodes. In order to discuss the channel formation and FET characteristics, we observed the typical current-voltage characteristics and calculated the threshold voltage of the CuPc FET device. We also found that the capacitance reached approximately 97 pF at a negative applied voltage and increased upon the accumulation of carriers at the interface of the metal and the CuPc material. We observed the typical behavior of a FET when used as an n-channel FET. Moreover, we calculated the threshold voltage to be about 15-20 V at V_DS = -80 V.