• Applied Microscopy
• /
• v.50
• /
• pp.17.1-17.9
• /
• 2020

Recent advances in fabrication have enabled radial-junction architectures for cost-effective and high-performance optoelectronic devices. Unlike a planar PN junction, a radial-junction geometry maximizes the optical interaction in the three-dimensional (3D) structures, while effectively extracting the generated carriers via the conformal PN junction. In this paper, we report characterizations of radial PN junctions that consist of p-type Si micropillars created by deep reactive-ion etching (DRIE) and an n-type layer formed by phosphorus gas diffusion. We use electron-beam induced current (EBIC) microscopy to access the 3D junction profile from the sidewall of the pillars. Our EBIC images reveal uniform PN junctions conformally constructed on the 3D pillar array. Based on Monte-Carlo simulations and EBIC modeling, we estimate local carrier separation/collection efficiency that reflects the quality of the PN junction. We find the EBIC efficiency of the pillar array increases with the incident electron beam energy, consistent with the EBIC behaviors observed in a high-quality planar PN junction. The magnitude of the EBIC efficiency of our pillar array is about 70% at 10 kV, slightly lower than that of the planar device (≈ 81%). We suggest that this reduction could be attributed to the unpassivated pillar surface and the unintended recombination centers in the pillar cores introduced during the DRIE processes. Our results support that the depth-dependent EBIC approach is ideally suitable for evaluating PN junctions formed on micro/nanostructured semiconductors with various geometry.

• Journal of Korea Foundry Society
• /
• v.3 no.3
• /
• pp.174-180
• /
• 1983

The matrix changes and graphite formation in high manganese cast iron (Fe-12Mn-3.5C) are studied with increasing nickel and silicon content. Also, the decomposition of carbides and graphite precipitation are studied by adequate heat treatment.The results obtained in this work are as follows. 1. In high manganese cast iron, fine flakes graphite appeared by adding 5 wt% nickel and A-type flakes graphite can be obtained by adding 7 wt% nickel. 2. Nodular graphite are obtained by graphite spheroidizing treatment with same melt. 3. In high manganese cast iron containing 7 wt% nickel, full austenitic matrix with nodular graphite can be achieved by water quenching after 10 hours' solution heat treatment at $1050^{\circ}C$ in case of containing 2.0 wt% silicon, and 6 hours' at the same temperature in case of containing 2.5 wt% silicon.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.97-98
• /
• 2009

Tunneling barrier engineered charge trap flash (TBE-CTF) memory capacitor were fabricated using the tunneling barrier engineering technique. Variable oxide thickness (VARIOT) barrier and CRESTED barrier consisting of thin $SiO_2$ and $Si_3N_4$ dielectrics layers were used as engineered tunneling barrier. The charge trapping characteristic with different metal gates are also investigated. A larger memory window was achieved from the TBE-CTF memory with high workfunction metal gate.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2003.03a
• /
• pp.126-126
• /
• 2003

유기트랜지스터에 관한 연구는 1980년 이후부터 시작되었으나 근래에 들어 전 세계적으로 본격적인 연구가 진행되고 있다. 제작공정이 간단하고 비용이 저렴하며 충격에 의해 깨지지 않고 구부리거나 접을 수 있는 전자 회로 기판이 미래의 산업에 필수적인 요소가 될 것으로 예상되고 있으며 이러한 요구를 충족시킬 수 있는 유기트랜지스터의 개발은 아주 중요한 연구분야로 대두되고 있다. 본 연구에서는 표면처리에 따른 contact angle, I-V 특성곡선, 표면 morphology 등의 결과로부터 dry cleaning 한 것이 wet cleaning한 것보다 왜 좋은지를 논하고자 한다. 먼저 N-type SiO$_2$ 기판을 이용하여 back면의 oxide층을 제거한 후, back gate용으로 사용하기 위하여 sputtering장치로 Au/Cr을 증차하였다. 그리고 기판에 앞면을 photolithography 공정을 이용하여 Au/Cr를 1000$\AA$ 증착 하여 source-, drain-eldctrode를 제조하였다. 그리고 SiO$_2$ 기판의 표면처리를 달리하여 그 위에 유기박막을 증착하여 특성을 비교하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.23 no.3
• /
• pp.177-182
• /
• 2010

The pentacene-based organic thin film transistors(OTFTs) using polyvinylalcohol(PVA) alignment layer were fabricated on the $SiO_2$ evaporated to n-type (111) Si substrates. The pentacene film was deposited by thermally evaporated at $10^{-7}$ torr. X-ray diffraction (XRD) and atomic force microscope(AFM) measurement showed pentacene film which deposited on rubbed PVA layers were partially crystallized at (001) plane. The pentacene OTFTs with PVA layers rubbed perpendicular to the direction of current flow was shown to align better orientation than parallel rubbed case and thus to enhance the mobility and saturation current by a factor of 2.3 respectively. We obtained mobility by 0.026 $cm^2$/Vs and on-off current ratio by ${\sim}10^8$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1992.11a
• /
• pp.11-13
• /
• 1992

The dielectric reliability of the Thin $SiO_2$ films of wet oxidation on n-type Si substrates has been studied by using self-healing method of breakdown and according to injection time high frequence C-V tests. These experiments have been performed to investigate the dielectric breakdown mechanism of a thin film in which positive charge generation during high-field Fowler-Nordheim tunneling are considered. In addition, The weak spots and robust areas are distinguished so that the localized dielectric breakdown could be described.

• Journal of Information Display
• /
• v.8 no.4
• /
• pp.15-18
• /
• 2007

In this paper, we investigated the SLS process to control grain boundary(GB) location in TFT channel region, and it has been found to be applicable for locating the GB at the same location in the channel region of each TFT. We fabricated TFT by applying a new alignment SLS process and compared the TFT characteristics with a normal SLS method and the grain boundary location controlled SLS method. Also, we have analysed degradation phenomena under hot carrier stress conditions for n-type LDD MOSFETs.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.409-409
• /
• 2012

모바일 및 TV, 모니터 부분에서 AMOLED의 비약적인 시장 점유율 확대와 더불어 TFT 소자 부문에서도 많은 집중과 연구개발이 이루어지고 있다. 높은 이동도를 필요로 하는 AMOLED의 구동 회로에 채널층으로서 a-Si이 낮은 이동도로 인한 한계에 부딪히며 더 이상 쓰일 수 없게 되었고, 현재 우수한 이동도와 균일성, 제조 원가 절감의 효과 등 많은 장점을 보유한 산화물 TFT가 접목되고 있다. 현재까지 IGZO, ZnO 등이 많이 연구되며 실제로 AMOLED 용 TFT 소자에 적용 되고 있다. 본 연구에서는 산화물질인 ZTO (Zinc-Tin-Oxide)를 이용하여 TFT를 제작하였다. n-type 웨이퍼에 PECVD를 이용하여 $SiO_2$를 100 nm 증착한 뒤 spin coater로 ZTO용액을 30 nm 증착하였다. ZTO의 최적화된 열처리 온도인 $450^{\circ}C$에서 annealing을 해준 다음에 thermal evaporator로 source와 drain을 증착하였다. Gate 컨택을 위하여 웨이퍼 후면에 silver paste를 이용해 소자를 완성하였다. 산화물질 특성상 환경변화에 민감한 경향성을 보이기 때문에 현재 산화물 TFT는 신뢰성 분석에 많은 연구가 진행되고 있다. 완성된 ZTO TFT 소자를 빛과 수분에 일정한 시간 노출시킨 뒤 I-V 측정을 통하여 소자 열화를 분석하였다.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2002.05a
• /
• pp.92-97
• /
• 2002

We establish a visible light emission from porous polycrystalline silicon nano structure(PPNS). The PPNS layer are formed on heavily doped n-type Si substrate. 2um thickness of undoped polycrystalline silicon deposited using LPCVD (Low Pressure Chemical Vapor Deposition) anodized in a HF: ethanol(=1:1) as functions of anodizing conditions. And then a PPNS layer thermally oxidized for 1 hr at $900 ^{\circ}C$. Subsequently, thin metal Au as a top electrode deposited onto the PPNS surface by E-beam evaporator and, in order to establish ohmic contact, an thermally evaporated Al was deposited on the back side of a Si-substrate. When the top electrode biased at +6V, the electron emission observed in a PPNS which caused by field-induces electron emission through the top metal. Among the PPNSs as functions of anodization conditions, the PPNS anodized at a current density of $10mA/cm^2$ for 20 sec has a lower turn-on voltage and a higher emission current. Furthermore, the behavior of electron emission is uniformly maintained.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1999.11a
• /
• pp.453-456
• /
• 1999

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor)NVSM(nonvolatile semiconductor memory) cell were investigated by single charge pumping method. The used device was fabricated by 0.35 7m standard logic fabrication including the ONO cell process. This ONO dielectric thickness is tunnel oxide 24 $\AA$, nitride 74 $\AA$, blocking oxide 25 $\AA$, respectively. Keeping the pulse base level in accumulation and pulsing the surface into inversion with increasing amplitudes, the charge pumping current flow from the single junction. Using the obtained I$_{cp}$-V$_{h}$ curve, the local V$_{t}$ distribution, doping concentration, lateral interface trap distribution and lateral memory trap distribution were extracted. The maximum N$_{it}$($\chi$) of 1.62$\times$10$^{19}$ /cm$^2$were determined.mined.d.