• Title/Summary/Keyword: multistandard

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A 85-mW Multistandard Multiband CMOS Mobile TV Tuner for DVB-H/T, T-DMB, and ISDB-T Applications with FM Reception

  • Nam, Ilku;Bae, Jong-Dae;Moon, Hyunwon;Park, Byeong-Ha
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.3
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    • pp.381-389
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    • 2015
  • A fully integrated multistandard multiband CMOS mobile TV tuner with small silicon area and low power consumption is proposed for receiving multiple mobile digital TV signals and FM signal. In order to reduce the silicon area of the multistandard multiband receiver, other RF front-end circuits except LNAs are shared and a local oscillator (LO) signal generation architecture with a single VCO for a frequency synthesizer is proposed. To reduce the low frequency noise and the power consumption, a vertical NPN BJT is used in an analog baseband circuits. The RF tuner IC is implemented in a $0.18-{\mu}m$ CMOS technology. The RF tuner IC satisfies all specifications for DVB-H/T, T-DMB, and ISDB-T with a sufficient margin and a successful demonstration has been carried out for DVB-H/T, T-DMB, and ISDB-T with a digital demodulator.

Double-Sharpened Decimation Filter Employing a Pre-droop Compensator for Multistandard Wireless Applications

  • Jeong, Chan-Yong;Min, Young-Jae;Kim, Soo-Won
    • ETRI Journal
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    • v.33 no.2
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    • pp.169-175
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    • 2011
  • This paper presents a double-sharpened decimation filter based on the application of a Kaiser and Hamming sharpening technique for multistandard wireless systems. The proposed double-sharpened decimation filter uses a pre-droop compensator which improves the passband response of a conventional cascaded integrator-comb filter so that it provides an efficient sharpening performance at half-speed with comparison to conventional sharpened filters. In this paper, the passband droop characteristics with compensation provides -1.6 dB for 1.25 MHz, -1.4 dB for 2.5 MHz, -1.3 dB for 5 MHz, and -1.0 dB for 10 MHz bandwidths, respectively. These results demonstrate that the proposed double-sharpened decimation filter is suitable for multistandard wireless applications.

A multistandard CMOS mixer using switched inductor (스위칭 인덕터를 이용한 다중 표준용 CMOS 주파수 변환기)

  • Yoo, Sang-Sun;Yoo, Hyung-Joun
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.44 no.3 s.357
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    • pp.78-84
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    • 2007
  • A multistandard direct-conversion mixer for WCDMA, Wibro, and 802.11a/b/g is designed in 0.18 um CMOS technology To support multistandard and to reduce the chip area the switched inductor is used as the matching method. This switched inductor matching network selects the mixer's operation frequency band by turning on or off the switch transistor. Since the performances of mixer and operation frequency can be affected by the parasitic of switch transistor the mixer should be designed with the optimized size of switch to minimize parasitic effects. Proposed mixer is able to achieve return loss less than -13 dB in $2.1\sim2.5GHz$ and $5.1\sim5.9GHz$ bands with the suitable performance to meet requirements of WCDMA, WiBro, and 802.11a/b/g.

A Design of A Multistandard Digital Video Encoder using a Pipelined Architecture

  • Oh, Seung-Ho;Park, Han-Jun;Kwon, Sung-Woo;Lee, Moon-Key
    • Journal of Electrical Engineering and information Science
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    • v.2 no.5
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    • pp.9-16
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    • 1997
  • This paper describes the design of a multistandard video encoder. The proposed encoder accepts conventional NTSC/PAL video signals, It also processes he PAL-plus video signal which is now popular in Europe. The encoder consists of five major building functions which are letter-box converter, color space converter, digital filters, color modulator and timing generator. In order to support multistandard video signals, a programmable systolic architecture is adopted in designing various digital filters. Interpolation digital filters are also used to enhance signal-to-noise ratio of encoded video signals. The input to the encoder can be either YCbCr signal or RGB signal. The outputs re luminance(Y), chrominance(C), and composite video baseband(Y+C) signals. The architecture of the encoder is defined by using Matlab program and is modelled by using Veriflog-HDL language. The overall operation is verified by using various video signals, such as color bar patterns, ramp signals, and so on. The encoder contains 42K gates and is implemented by using 0.6um CMOS process.

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A 3.3-V Low-Power Compact Driver for Multi-Standard Physical Layer

  • Park, Joon-Young;Lee, Jin-Hee;Jeong, Deog-Kyoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.7 no.1
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    • pp.36-42
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    • 2007
  • A low-power compact driver for multistandard physical layer is presented. The proposed driver achieves low power and small area through the voltage-mode driver with trans-impedance configuration and the novel hybrid driver,. In the voltage-mode driver, a trans-impedance configuration alleviates the problem of limited common-mode range of error amplifiers and the area and power overhead due to pre-amplifier. For a standard with extended output swing, only current sources are added in parallel with the voltage-mode driver, which is named a 'hybrid driver'. The hybrid architecture not only increases output swing but reduces overall driver area. The overall driver occupies $0.14mm^2$. Power consumptions under 3.3-V supply are 24.5 mW for the voltage-mode driver and 44.5 mW for the hybrid driver.