• Bulletin of the Korean Mathematical Society
• /
• v.46 no.5
• /
• pp.857-866
• /
• 2009

Let n be a fixed positive integer, R be a 2n!-torsion free prime ring and $\mu$, $\nu$ be a pair of generalized derivations on R. If < $\mu^2(x)+\nu(x),\;x^n$ > = 0 for all x $\in$ R, then $\mu$ and $\nu$ are either left multipliers or right multipliers. Let n be a fixed positive integer, R be a noncommutative 2n!-torsion free prime ring with the center $C_R$ and d, g be a pair of derivations on R. If < $d^2(x)+g(x)$, $x^n$ > $\in$ $C_R$ for all x $\in$ R, then d = g = 0. Then we apply these purely algebraic techniques to obtain several range inclusion results of pair of (generalized-)derivations on a Banach algebra.

• Journal of the Korean Mathematical Society
• /
• v.55 no.3
• /
• pp.719-734
• /
• 2018

An image restoration problem with Poisson noise arises in many applications of medical imaging, astronomy, and microscopy. To overcome ill-posedness, Total Variation (TV) model is commonly used owing to edge preserving property. Since staircase artifacts are observed in restored smooth regions, higher-order TV regularization is introduced. However, sharpness of edges in the image is also attenuated. To compromise benefits of TV and higher-order TV, the weighted sum of the non-convex TV and non-convex higher order TV is used as a regularizer in the proposed variational model. The proposed model is non-convex and non-smooth, and so it is very challenging to solve the model. We propose an iterative reweighted algorithm with the proximal linearized alternating direction method of multipliers to solve the proposed model and study convergence properties of the algorithm.

• Journal of the Korean Mathematical Society
• /
• v.38 no.1
• /
• pp.1-23
• /
• 2001

This paper is concerned with an optimal shape control problem for the stationary Navier-Stokes system. A two-dimensional channel flow of an incompressible, viscous fluid is examined to determine the shape of a bump on a part of the boundary that minimizes the viscous drag. by introducing an artificial compressibility term to relax the incompressibility constraints, we take the penalty method. The existence of optima solutions for the penalized problem will be shown. Next, by employing Lagrange multipliers method and the material derivatives, we derive the shape gradient for the minimization problem of the shape functional which represents the viscous drag.

• Proceedings of the KIEE Conference
• /
• 2005.07d
• /
• pp.3058-3060
• /
• 2005

In this paper, the CMOS four-quadrant analog multipliers for low-voltage low-power applications are presented. The circuit approach is based on the characteristic of the LV (Low-Voltage) composite transistor which is one of the useful analog building blocks. SPICE simulations are carried out to examine the performances of the designed multipliers. Simulation results are obtained by $0.25{\mu}m$ CMOS parameters with 2V power supply. The LV composite transistor can easily be extended to perform a four-quadrant multiplication. The multiplier has a linear input range up to ${\pm}0.5V$ with a linearity error of less than 1%. The measured -3dB bandwidth is 290MHz and the power dissipation is $37{\mu}W$. The proposed multiplier is expected to be suitable for analog signal processing applications such as portable communication equipment, radio receivers, and hand-held movie cameras.

• Journal of the Korean Operations Research and Management Science Society
• /
• v.15 no.1
• /
• pp.99-115
• /
• 1990

This paper is concerned with the unit commitment problem in an electric power system with both thermal and pumped-storage hydroelectric units. This is a mixed integer programming problem and the Lagrangean relaxation method is used. We show that the relaxed problem decomposes into two kinds of subproblems : a shortest-path problem for each thermal unit and a minimum cost flow problem for each pumped-storage hydroelectric unit. A method of obtaining an incumbenet solution from the solution of a relaxed problem is presented. The Lagrangean multipliers are updated using both subgradient and incremental cost. The algorithm is applied to a real Korean power generation system and its computational results are reported and compaired with other works.

• Proceedings of the KIEE Conference
• /
• summer
• /
• pp.15-17
• /
• 2004

The flexible AC transmissions system (FACTS) is the underpinning concept upon which are based promising means to avoid effectively power flow bottlenecks and ways to extend the loadability of existing power transmission networks. This paper proposes a method by which the optimal locations of the FACTS to be installed in power system under cost function. The optimal solution of this type of problem requires large scale nonlinear optimisation techniques. We used Lagrange multipliers to solve a nonlinear equation with equality and ineaquality constraints. Case studies on the standard IEEE 14 bus system show that the method can be implemented successfully and that it is effective for determining the optimal location of the FACTS

• Journal of the Korean Society for Industrial and Applied Mathematics
• /
• v.18 no.1
• /
• pp.17-26
• /
• 2014

This paper presents development of an improved domain decomposition method for large scale structural problem that aims to provide high computational efficiency. In the previous researches, we developed the domain decomposition algorithm based on augmented Lagrangian formulation and proved numerical efficiency under both serial and parallel computing environment. In this paper, new computational analysis by the proposed domain decomposition method is performed. For this purpose, reduction in computational time achieved by the proposed algorithm is compared with that obtained by the dual-primal FETI method under serial computing condition. It is found that the proposed methods significantly accelerate the computational speed for a linear structural problem.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.11
• /
• pp.152-161
• /
• 1996

This paper descrisbes the implementation of a 20D DCT that can be used for video conference, JPEG, and MPEG-related applications. The implemented DCT consists of two 1-D DCTs and a transposed memory between them, and uses ROM-based multipliers instead of conventional ones. As the system bit length, the minimum bit length that satisfies the accuracy specified by the ITU standard H.261 was chosen through the simulations using the C language. The proposed design uses a dual port RAM for the transposed memory, and processes two bits of input-pixel data simultaneously t ospeed up addition process using two sets of ROMs. The basic system architecture was designed using th Synopsys schematic editor, and internal modules were described in VHDL and synthesized to logic level after simulation. Then, the compass silicon compiler was used to create the final lyout with 0.8um CMOS libraries, using the standard cell approach. The final layout contains about 110, 000 transistors and has a die area of 4.68mm * 4.96mm, and the system has the processing speed of about 50M pixels/sec.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.19 no.1
• /
• pp.59-63
• /
• 2005

In this article, we apply the standard method of Lagrange multipliers to examine the algorithm in a recent IEEE publication which calculates the optimal generation for minimizing the system loss using loss sensitivities derived by angle reference transposition, and show that the two algorithms are mathematically the same.

• ETRI Journal
• /
• v.19 no.4
• /
• pp.317-325
• /
• 1997

A new on-the-fly conversion algorithm is proposed, and high-speed array multipliers with the on-the-fly conversion are presented. The new on-the-fly conversion logic is used to speed up carry-propagate addition at the last stage of multiplication, and provides constant delay independent of the number of input bits. In this paper, the multiplication architecture and the on-the-fly conversion algorithm are presented and discussed in detail. The proposed architecture has multiplication time of (n +1)$t_{FA}$, Where n is the number of input bits and $t_{FA}$ is the delay of a full adder. According to our comparative performance evaluation, the proposed architecture has shorter delay and requires less area than the conventional array multiplier with on-the-fly conversion.