• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.6
• /
• pp.20-29
• /
• 1998

This paper proposes the algorithms that design the highly parallel multiple-valued logic curcuit and assign the code to each node of DCG(Directed Cyclic Graph) of length 1. The conventional Nakajima's algorithm have some problems, so this paper introduce the matrix equation from DCG of length 1 and proposes circuit design algorithms according to the DCG of length 1. Using the proposed circuit design algorithms in this paper, it become realized that was not able to design from Nakajima's algorithm. Also, making a comparision between the circuit design using Nakajima's algorithm and this paper's, we testify that proposed paper's algorithm is able to realize more optimized circuit design. According to proposed curcuit design algorithm in this paper, it is possible to design curcuit that DCG have natural number, so it have the following advantages; reduction of the curcuit input/output digits, simplification of curcuit composition, reduction of computation time and cost. And we show compatibility and verification about this paper's algorithm.

• Journal of IKEEE
• /
• v.9 no.1 s.16
• /
• pp.1-6
• /
• 2005

This paper proposes a high performance multiplier using CMOS multiple-valued logic circuits. The multiplier based on the Modified Baugh-Wooley algorithm is designed with current-mode CMOS quaternary logic circuits. The multiplier is functionally partitioned into the following major sections: partial product generator block(binary-quaternary logic conversion block), current-mode quaternary logic full-adder block, and quaternary-binary logic conversion block. The proposed multiplier has 4.5ns of propagation delay and 6.1mW of power consumption. This multiplier can easily adapted to the binary system by the encoder and the decoder. This circuit is designed with 0.35um standard CMOS process at 3.3V supply voltage and 5uA unit current. The validity and effectiveness are verified through the HSPICE simulation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• v.9 no.1
• /
• pp.126-130
• /
• 2005

In this paper, a low-complexity maximum-likelihood (ML) decoder based on QR decomposition, called real-valued LCMLDec decoder or RVLCMLDec for short, is proposed for the Vertical Bell Labs Layered Space-Time (V-BLAST) architecture, a promising candidate for providing high data rates in future fixed wireless communication systems [1]. Computer simulations, in comparison with other detection techniques, show that the proposed decoder is capable of providingthe V-BLAST schemes with ML performance at low detection complexity.

• Journal of information and communication convergence engineering
• /
• v.3 no.2
• /
• pp.76-79
• /
• 2005

In this paper, a low-complexity maximum-likelihood (ML) decoder based on QR decomposition, called real-valued LCMLDec decoder or RVLCMLDec for short, is proposed for the Vertical Bell Labs Layered Space-Time (V-BLAST) architecture, a promising candidate for providing high data rates in future fixed wireless communication systems [1]. Computer simulations, in comparison with other detection techniques, show that the proposed decoder is capable of providing the V­BLAST schemes with ML performance at low detection complexity

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.8 no.8
• /
• pp.2607-2625
• /
• 2014

Previous studies on multiuser multiple-input multiple-output (MIMO) mostly assume a homogeneous signal-to-noise ratio (SNR), where each user has the same average SNR. However, real networks are more likely to feature heterogeneous SNRs (a random-valued average SNR). Motivated by this fact, we analyze a multiuser MIMO downlink with a zero-forcing (ZF) receiver in a heterogeneous SNR environment. A transmitter with Mantennas constructs M orthonormal beams and performs the SNR-based proportional fairness (S-PF) scheduling where data are transmitted to users each with the highest ratio of the SNR to the average SNR per beam. We develop a new analytical expression for the sum throughput of the multiuser MIMO system. Furthermore, simply modifying the expression provides the sum throughput for important special cases such as homogeneous SNR, max-rate scheduling, or high SNR. From the analysis, we obtain new insights (lemmas): i) S-PF scheduling maximizes the sum throughput in the homogeneous SNR and ii) under high SNR and a large number of users, S-PF scheduling yields the same multiuser diversity for both heterogeneous SNRs and homogeneous SNRs. Numerical simulation shows the interesting result that the sum throughput is not always proportional to M for a small number of users.

• Journal of the Optical Society of Korea
• /
• v.20 no.4
• /
• pp.476-480
• /
• 2016

For the application of multiusers, the arrangement and distribution of the keys is a much concerning problem in a cryptosystem. In this paper, we propose an optical encryption scheme with multiple users based on computational ghost imaging (CGI) and orthogonal modulation. The CGI encrypts the secret image into an intensity vector rather than a complex-valued matrix. This will bring convenience for post-processing and transmission of the ciphertext. The orthogonal vectors are taken as the address codes to distinguish users and avoid cross-talk. Only the decryption key and the address code owned by an authorized user are matched, the secret image belonging to him/her could be extracted from the ciphertext. Therefore, there are two security levels in the encryption scheme. The feasibility and property are verified by numerical simulations.

• Journal of the Korean Society of Food Culture
• /
• v.36 no.6
• /
• pp.531-541
• /
• 2021

This study was conducted to provide basic data for evolving a strategy for the development of Vietnam's customized HMR program and formulating a marketing strategy by analyzing the characteristics and variations of HMR consumption behavior by household size. The results of the analysis were as follows: The number of single households using HMR as a general meal at home was higher than multiple-person households. Moreover, there was a high preference for 'ready to heat' and 'ready to eat' products, which are relatively easy to cook and prepare. It was observed that single households preferred department stores, hypermarkets, and convenience stores for purchasing HMR when compared to multiple households, and that single households preferred to acquire information through TV/radio and internet advertisements. Among the HMR selection attributes, single households valued taste, quantity, price, preparation process, preparation time, and ease of storage as important. Reflecting on the results of this study, when developing HMR in Vietnam, it is necessary to develop a product that can nutritionally replace the general meal with a focus on convenience. In addition, there is a need for products that possess various attributes such as convenience, health, and eco-friendliness.

• Journal of Communications and Networks
• /
• v.13 no.5
• /
• pp.481-493
• /
• 2011

Multiple-input multiple-output (MIMO) technology provides high data rate and enhanced quality of service for wireless communications. Since the benefits from MIMO result in a heavy computational load in detectors, the design of low-complexity suboptimum receivers is currently an active area of research. Lattice-reduction-aided detection (LRAD) has been shown to be an effective low-complexity method with near-maximum-likelihood performance. In this paper, we advocate the use of systolic array architectures for MIMO receivers, and in particular we exhibit one of them based on LRAD. The "Lenstra-Lenstra-Lov$\acute{a}$sz (LLL) lattice reduction algorithm" and the ensuing linear detections or successive spatial-interference cancellations can be located in the same array, which is considerably hardware-efficient. Since the conventional form of the LLL algorithm is not immediately suitable for parallel processing, two modified LLL algorithms are considered here for the systolic array. LLL algorithm with full-size reduction-LLL is one of the versions more suitable for parallel processing. Another variant is the all-swap lattice-reduction (ASLR) algorithm for complex-valued lattices, which processes all lattice basis vectors simultaneously within one iteration. Our novel systolic array can operate both algorithms with different external logic controls. In order to simplify the systolic array design, we replace the Lov$\acute{a}$sz condition in the definition of LLL-reduced lattice with the looser Siegel condition. Simulation results show that for LR-aided linear detections, the bit-error-rate performance is still maintained with this relaxation. Comparisons between the two algorithms in terms of bit-error-rate performance, and average field-programmable gate array processing time in the systolic array are made, which shows that ASLR is a better choice for a systolic architecture, especially for systems with a large number of antennas.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.12 no.10
• /
• pp.4814-4834
• /
• 2018

This paper presents an architecture for wireless sensor networks (WSNs) with blind source separation (BSS) applied to retrieve the received mixing signals of the sink nodes first. The little-to-no need of prior knowledge about the source signals of the sink nodes in the BSS method is obviously advantageous for WSNs. The optimization problem of the BSS of multiple independent source signals with complex and noncircular distributions from observed sensor nodes is considered and addressed. This paper applies Castella's reference-based scheme to Novey's negentropy-based algorithms, and then proposes a novel fast fixed-point (FastICA) algorithm, defined as the reference-signal negentropy complex FastICA (RSNT-cFastICA) for complex-valued noncircular-distribution source signals. The proposed method for the sink nodes is substantially more efficient than Novey's quasi-Newton algorithm in terms of computational speed under large numbers of samples, can effectively improve the power consumption effeciency of the sink nodes, and is significantly beneficial for WSNs and wireless communication networks (WCNs). The effectiveness and performance of the proposed method are validated and compared with three related BSS algorithms through theoretical analysis and simulations.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.723-726
• /
• 2005

GALS (Globally Asynchronous Locally Synchronous) 시스템 기반의 SoC 설계에 필수적인 DI (Delay Insensitive) 데이터 전송방식 중 기존의 전압 모드 기반 설계 방식은 N 비트 데이터 전송에 물리적으로 2N+1 개의 도선이 필요하다. 이로 인한 전력 소모와 설계 복잡성을 줄이기 위해 N+1 개의 도선으로 N 비트 데이터를 전송할 수 있는 전류 모드 다치 논리 회로 기반 설계 방식이 연구되었다. 그러나, static 전력의 비중이 커 데이터 전송 속도가 낮을수록 전력 소모 측면에서 취약하고, 휴지 모드에서도 상당량의 전력을 소비한다. 본 논문에서는 이러한 문제점을 해결할 수 있는 전류 모드 기반 인코더와 디코더 회로를 제안하고, 이에 따른 새로운 전류 인코딩 기법을 설명한다. 마지막으로 기존의 전압 모드 및 전류 모드 방식과 delay, 전력 소비 측면에서 비교 데이터를 제시한다.