• Journal of Power Electronics
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• 제14권2호
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• pp.292-301
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• 2014

This paper presents a new configuration for a three-phase multilevel voltage source inverter. The main bridge is built from a classical three-phase two-level inverter and three bidirectional switches. A variable DC-link employing two unequal DC voltage supplies and four switches is connected to the main circuit in such a way that the proposed inverter produces four levels in the output voltage waveform. In order to obtain the desired switching gate signals, the fundamental frequency staircase modulation technique is successfully implemented. Furthermore, the proposed structure is extended and compared with other types of multilevel inverter topologies. The comparison shows that the proposed inverter requires a smaller number of power components. For a given number of voltage steps N, the proposed inverter requires N/2 DC voltage supplies and N+12 switches connected with N+7 gate driver circuits, while diode clamped or flying capacitor inverters require N-1 DC voltage supplies and 6(N-1) switches connected with 6(N-1) gate driver circuits. A prototype of the introduced configuration has been manufactured and the obtained simulation and experimental results ensure the feasibility of the proposed topology and the validity of the implemented modulation technique.

• Journal of Power Electronics
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• 제14권4호
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• pp.671-677
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• 2014

In this paper, a new basic unit is proposed. Then, a cascaded multilevel inverter basded on the series connection of n number of these new basic units is proposed. In order to generate all of the voltage levels (even and odd) at the output, three different algorithms to determine the magnitude of the dc voltage source are proposed. Reductions in the number of power switches, driver circuits and dc voltage sources in addition to increases in the numbr of output voltage levels are some of the advantages of the proposed cascaded multilevel inverter. These results are obtained through a comparison of the proposed inverter and its algorithms with an H-bridge cascaded multilevel inverter from the point of view of the number of power electronic devices. Finally, the capability of the proposed topology with its proposed algorithms in generating all of the voltage levels is verified through experimental results on a laboratorary prototype of a 49-level inverter.

• Journal of Power Electronics
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• 제14권1호
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• pp.48-60
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• 2014

Multilevel inverters have been widely used for high-voltage and high-power applications. Their performance is greatly superior to that of conventional two-level inverters due to their reduced total harmonic distortion (THD), lower switch ratings, lower electromagnetic interference, and higher dc link voltages. However, they have some disadvantages such as an increased number of components, a complex pulse width modulation control method, and a voltage-balancing problem. In this paper, a novel nine-level reduced switch cascaded multilevel inverter based on a multilevel DC link (MLDCL) inverter topology with reduced switching components is proposed to improve the multilevel inverter performance by compensating the above mentioned disadvantages. This topology requires fewer components when compared to diode clamped, flying capacitor and cascaded inverters and it requires fewer carrier signals and gate drives. Therefore, the overall cost and circuit complexity are greatly reduced. This paper presents modulation methods by a novel reference and multicarrier based PWM schemes for reduced switch cascaded multilevel inverters (RSCMLI). It also compares the performance of the proposed scheme with that of conventional cascaded multilevel inverters (CCMLI). Simulation results from MATLAB/SIMULINK are presented to verify the performance of the nine-level RSCMLI. Finally, a prototype of the nine-level RSCMLI topology is built and tested to show the performance of the inverter through experimental results.

• Journal of Power Electronics
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• 제13권5호
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• pp.787-797
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• 2013

Despite the advantages offered by multilevel inverters, one of the main drawbacks that prevents their widespread use is their circuit complexity as the number of power switches employed is usually high. This paper presents a new multilevel inverter topology with a considerable reduction in the number of power switches used through the switch-sharing approach. The fact that the proposed inverter applies two bidirectional power switches for sharing among the three phases does not prevent it from producing seven levels in the line-to-line output voltage waveforms. A modified scheme of space vector modulation via the application of virtual voltage vectors is developed to generate the PWM signals of the power switches. The performance of the proposed inverter is investigated through MATLAB/SIMULINK simulations and is practically tested using a laboratory prototype with a DSP-based modulator. The results demonstrate the satisfactory performance of the inverter and verify the effectiveness of the modulation method.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권1호
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• pp.58-69
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• 2016

This paper describes the design and implementation of a new diode clamped multilevel inverter for variable frequency drive. The diode clamp multilevel inverter has been widely used for low power, high voltage applications due to its superior performance. However, it has some limitations such as increased number of switching devices and complex PWM control. In this paper, a new topology is proposed. New topology requires only (N-1) switching devices and (N-3) clamping diodes compared to existing topology. A modified APO-PWM control method is used to generate gate pulses for inverter. The proposed inverter topology is coupled with single phase induction motor and its performance is tested by MATLAB simulation. Finally, a prototype model has built and its performance is tested with single phase variable frequency drive.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제51권11호
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• pp.645-651
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• 2002

In this paper, a multilevel PWM inverter employing a cascaded transformer is presented to reduce the harmonics of output voltage and load currents. The proposed PWM inverter consists of two full-bridge modules and their corresponding transformers. The secondarics of each transformer are series-connected. So continuous output voltage levels can be synthesized from the suitable selection of the turns ratio of trasformer. And it appears an integral ratio to input DC source. Because of the cascaded connection of transformers, output filter inductor is not necessary. The operational principles and analysis are explained, and it is compared with a conventional isolated H-bridge PWM inverter. The validity of proposed multilevel inverter is verified through simulated and experimental waveform and their FFT results.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제50권9호
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• pp.459-466
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• 2001

This paper proposes a snubber circuit for flying capacitor multilevel inverter and converter. The proposed snubber circuit makes use of Undeland snubber as basic snubber unit. It has such an advantage of Undeland snubber used in the two-level inverter. Compared with conventional RCD/RLD snubber for multileve1 inverter and converter, the proposed snubber keeps such good features as fewer number of components, reduction of voltage stress of main switching devices due to low overvoltage, and improved efficiency of system due to low loss snubber. In this paper, the proposed snubber is applied to three-level flying capacitor inverter and this feature is demonstrated by computer simulation and experimental result.

• Journal of Power Electronics
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• 제17권3호
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• pp.777-787
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• 2017

A new single phase half-bridge cascaded multilevel inverter based series active power filter (SAPF) is proposed. The main parts of the inverter are presented in detail. With the proposed inverter topology, any compensation voltage reference can be easily obtained. Therefore, the inverter acts as a harmonic source when the reference is a non-sinusoidal signal. A 31-level inverter based SAPF with the proposed topology, is manufactured and the voltage harmonics of the load connected to the point of common coupling (PCC) are compensated. There is no need for a parallel passive filter (PPF) since the main purpose of the paper is to represent the compensation capability of the SAPF without a PPF. It is aimed to compensate the voltage harmonics of the load fed by a non-sinusoidal supply using the proposed inverter. The validity of the proposed inverter based SAPF is verified by simulation as well as experimental study. The system efficiency is also measured in this study. Both simulation and experimental results show that the proposed multilevel inverter is suitable for SAPF applications.

• Journal of Electrical Engineering and Technology
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• 제10권1호
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• pp.261-270
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• 2015

In this paper, the Optimal Harmonic Stepped Waveform (OHSW) method is proposed in order to eliminate the selective harmonic orders available at the output of cascaded multilevel inverter (CMLI) fed by solar photovoltaic (SPV). This technique is used to solve the harmonic elimination equations based on stepped waveform analysis in order to obtain the optimal switching angles which in turn reduce the Total Harmonic Distortion (THD). The OHSW method considers the output voltage waveform as four equal symmetries in each half cycle. In the proposed method, a solar fed fifteen level cascaded multilevel is considered where the magnitude of six numbers of harmonic orders is reduced. A programmable pulse generator is developed to carry the switching angles directly to the semiconductor switches obtained as a result of OHSW analysis. Simulations are carried out in MATLAB/Simulink in which a separate model is developed for solar photovoltaic which serves as the input for cascaded multilevel inverter. A 3kWp solar plant with multilevel inverter system is implemented in hardware to show the effectiveness of the proposed system. Based on the observation the OHSW method provides the reduced THD thereby improving power quality in renewable energy applications.

• 조명전기설비학회논문지
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• 제28권10호
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• pp.16-26
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• 2014

This paper proposes new 13-level inverter topology and DC/DC converter buck-boost structure topology for multilevel, compounding uni-directional and bi-directional switches, and proposes high-efficient multilevel inverter system in which the proposed two PCS(Power Conditioning System) was connected in series. In proposed multilevel inverter of forming a output 13-level phase voltage by using total 18 switching parts, Then bi-directional switch has a characteristic of reducing conduction loss and controlling the reactive power effectively by separating electrically from the neutral point. DC/DC converter for supplying in dependent 3 DC voltage to the proposed multi-level inverter generates 180-degree phase shifted PWM by the symmetrically combined structure of 2 buck-boost converter and twice switching frequency efficiency can be obtained, meanwhile, the converter can step up/down the output voltage and 20% output can be generated comparing the input voltage. This proposed system is verified with the simulation and laboratory test.