• 한국컴퓨터정보학회논문지
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• 제21권5호
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• pp.49-56
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• 2016

Increasing Internet traffic and forwarding table size need high performance IP address lookup engine which is a crucial function of routers. For finding the longest matching prefix, trie-based or its variant schemes have been widely researched in software-based IP lookup. As a software router, we enhance the IP address lookup engine using GPU which is a device widely used in high performance applications. We propose a data structure for multibit trie to exploit GPU hardware efficiently. Also, we devise a novel scheme that the root subtrie is loaded on Shared Memory which is specialized for fast access in GPU. Since the root subtrie is accessed on every IP address lookup, its fast access improves the lookup performance. By means of the performance evaluation, our implemented GPU-based lookup engine shows 17~23 times better performance than CPU-based engine. Also, the fast access technique for the root subtrie gives 10% more improvement.

• 전자공학회논문지A
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• 제32A권5호
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• pp.71-80
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• 1995

The usual approach for desinging a fast multiplier involves finding a way to quickly add up all the partial products, based on parital product recoding scheme and carry-save addition. This paper describes theoretical medels for area and time complexities of Multibit Reconding Paralle Multiplier (MRPM), which is a generalization of the modified Booth recoding scheme. Based on the proposed models, time performance, hardware requirements and area-time efficiency are analyzed in order to determine optimal recoding size for very large scale integration (VLSI) realization of the MRPM. Some simulation results show that the MRPM with large multiplier and multiplicand size has optimal area-time efficiency at the recoding size of 4-bit.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 추계학술대회 논문집 학회본부
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• pp.489-492
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• 1995

This paper has represented the new system for a multibit oversampled sigma-delta A/D convertor. The novel digital correction scheme with the ROM-Table is employed to enhance SNR without requiring accurate precision of the analogue components. This architectures have a good features compared with the 1-bit approach, including significantly lower quantization noise for a given oversampling ratio, as well as improved stability characteristics. Then we have shown the validity of the proposed system by use of the software for the performance evaluation and by realizing the system with SCFs(switched capacitor filter).

• 전자공학회논문지C
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• 제34C권1호
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• pp.21-27
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• 1997

We have proposed a new structure of the multibit ovesampling sigma-delta modulator. To solve the problkem of requring the accurate precision of the analog components, the novel digital correction scheme with a ROM-table has been employed to enhance the SNR for the proposed system. This architecture has good features compared with the 1-bit approach, including significantly lower quantisation noise for a given oversampling ratio, as well as improve dstability characteristics. Then we hve shown the validity of the proposed system by use of the software developed for the performance evaluation and by realizing the system with SCFs(switched capacitor filters).

• 전기학회논문지P
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• 제59권4호
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• pp.401-404
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• 2010

In multibit Sigma-Delta Modulator, DWA(Data Weighted Averaging) among the DEM(Dynamic Element Matching) techniques was widely used to get rid of non-linearity that caused by mismatching of unit capacitor in feedback DAC path. this paper proposed the improved DWA architecture by adjusting clock timing of the existing DWA architecture. 2n Register block used for output was replaced with 2n S-R latch block. As a result of this, MOS Tr. can be reduced and extra clock can also be removed. Moreover, two n-bit Register block used to delay n-bit data code is decreased to one n-bit Register. In order to confirm characteristics, DWA for the 3-bit output with the proposed DWA architecture was designed on 0.18um process under 1.8V supply. Compared with the existing architecture. It was able to reduce the number of 222 MOS Tr.

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2010년도 임시총회 및 하계학술연구발표회
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• pp.164-164
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• 2010

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2008년도 Asian Magnetics Conference
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• pp.17.1-17.1
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• 2008

• 대한전자공학회논문지SD
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• 제48권5호
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• pp.18-24
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• 2011

DEM(Dynamic Element Matching) 기법중의 하나인 DWA(Data Weighted Averaging)는 멀티비트 Sigma-Delta Modulator에서 피드백 DAC의 단위요소 커패시터 부정합으로 인한 비선형성을 제거하기 위하여 널리 이용된다. 본 논문에서는 기존 DWA 구조에서 적용된 클록 타이밍을 조정하여 양자화기 데이터 코드 출력을 Latch 하는 $2^n$ Register 블록을 $2^n$ S-R latch 블록으로 대체하여 MOS Tr.를 줄임과 더불어 여분의 클록을 제거하였고, n-bit 데이터 코드를 지연시키기 위해 사용되는 2개의 n-비트 Register 블록을 1개의 n-비트 Register 블록으로 감소시켰다. 개선된 DWA 구조를 이용하여 3차 3-비트 SC(Switched Capacitor) Sigma-Delta Modulator를 설계한 후, 입력 주파수 20kHz, 샘플링 주파수 2.56MHz에서 0.1% DAC 단위 요소 커패시터 부정합을 갖도록 하여 시뮬레이션 한 결과 기존의 구조와 동일한 해상도를 얻을 수 있었고, 222개의 MOS Tr. 수를 줄일 수 있었다.

• 한국통신학회논문지
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• 제15권2호
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• pp.166-175
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• 1990

기존 FIR 필터에는 回路가 複雜하고 高價의 乘算器가 많이 所要되기 때문에 實現에 제약을 받는다. 本 論文에서는 小型, 低價, 低電力消費, 高速 디지털필터로 實現하기에 적합하면서 乘算器를 사용하지 않는 FIR 필터 構造를 제시한다. 그 構造는 {0,{\pm}$2^n$;n=integer} 에서 두 개의 원소조합으로 표시되는 係數를 갖는 트랜스버설필터와 積分器로 구성된다. 컴퓨터 시뮬레이션에 의해 성능을 검토하였는바, 기존의 有限語長 FIR 필터의 경우와 비교하여 유사한 정도의 양호한 應答特性이 나타났다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 B
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• pp.361-364
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• 2003

In this paper, a high-resolution multibit sigma-delta modulator implemented in a.0.35-um CMOS technology is introduced. This modulator consists of two switched capacitor integrators, 3-bits A/D converter, and 3-bits D/A converter For the verification of the internal function blocks, HSPICE simulator is used. This circuit is normally operated at 130 MHz clock and the total power dissapation is 70 mW.