• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.701-704
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• 2011

The reliability of a computer system largely depends on that of its memory systems, which are vulnerable to soft errors. Soft errors can be coped with a combination of an Error Detection & Correction circuit and scrubbing operation. Smaller geometries and lower voltage of advanced memories makes them more prone to suffer multibit soft errors. A memory structure against multibit soft errors and a suitable scrubbing scheme for it were proposed. This paper introduces a key issue for the scrubbing of the memories with protection against multibit soft errors and the result of the performance analysis from a reliability point of view.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.4
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• pp.1922-1940
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• 2019

IP address lookup is a function to determine nexthop for a given destination IP address. It takes an important role in modern routers because of its computation time and increasing Internet traffic. TCAM-based IP lookup approaches can exploit the capability of parallel searching but have a limitation of its size due to latency, power consumption, updatability, and cost. On the other hand, multibit trie-based approaches use SRAM which has relatively low power consumption and cost. They reduce the number of memory accesses required for each lookup, but it still needs several accesses. Moreover, the memory efficiency and updatability are proportional to the number of memory accesses. In this paper, we propose a novel architecture using an Indexed Multibit Trie (IMT) which is based on combined TCAM and SRAM. In the proposed architecture, each lookup takes at most two memory accesses. We present how the IMT is constructed so as to be memory-efficient and fast updatable. Experiment results with real-world forwarding tables show that our scheme achieves good memory efficiency as well as fast updatability.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.9
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• pp.650-656
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• 2004

This paper presents block and timing diagrams of the DWA(data weighted averaging) to optimize a feedback time delay of the sigma-delta modulator. Through the Matlab modeling, the optimized coefficients of the integrators are obtained to design the modulator. And then the fully differential SC integrators, feedback DAC, 9-level quantizer, and DWA are designed by considering the nonideal characteristics of the modulator. The designed second-order multibit modulator is fabricated in a 0.35$\mu\textrm{m}$ CMOS process. The designed modulator achieves 73dB signal-to-noise ratio and 72dB dynamic range at 1.2Vp-p 585kHz input singal and 52.8MHz sampling frequency.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.4
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• pp.30-38
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• 1994

In this paper, we propose the parallel scrambling technique which is applicable in the multibit-interleaved multiplexing environment. For this, we introduce the concept of SSRG (simple shift register generator) and MSRG(modular shift register generator), and investigate their properties. We also introduce the concept of PSRG(parallel shift register generator) - parallel form of shift register generator, and consider realizations of PSRGs based on SSRGs and MSRGs. Finally, we show how to apply PSRGs to the parallel scrambling for the SDH system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1062-1070
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• 2002

In this paper, variable radix-two multibit coding algorithm is presented and applied in the implementation of discrete cosine transform(DCT) and inverse discrete cosine transform(IDCT). Variable radix-two multibit coding means the 2k SD (signed digit) representation of overlapped multibit scanning with variable shift method. SD represented by 2k generates partial products, which can be easily implemented with shifters and adders. This algorithm is most powerful for the hardware implementation of DCT/IDCT with constant coefficient matrix multiplication. This paper introduces the suggested algorithm, it's proof and the implementation of DCT/IDCT The implemented IDCT chip with 8 PEs(Processing Elements) and one transpose memory runs at a tate of 400 Mpixels/sec at 54MHz frequency for high speed parallel signal processing, and it's verified in HDTV and MPEG decoder.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.107-114
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• 2004

This paper presents block and timing diagrams of the DWA(Data Weighted Averaging) to optimize a feedback time delay of the sigma-delta modulator. Through the MATLAB modeling, the optimized coefficients of the integrators are obtained to design the modulator. The fully differential SC integrators, feedback DAC, 9-level quantizer, and DWA are designed by considering the nonideal characteristics of the modulator. The designed third-order multibit modulator is fabricated in a 0.35${\mu}{\textrm}{m}$ CMOS process. The modulator achieves 75dB signal-to-noise ratio and 74dB dynamic range at 1.2Vp-p 825kHz input signal and 52.8MHE sampling frequency.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.57-60
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• 2004

This paper presents multibit Sigma-Delta ADC using Leslie-Singh Structure to Improve nonlinearity of feedback loop. 4-bit flash ADC for multibit Quantization in Sigma Delta modulator offers the following advantages such as lower quantization noise, more accurate white-noise level and more stability over single quantization. For the feedback paths consisting of DAC, the DAC element should have a high matching requirement in order to maintain the linearity performance which can be obtained by the modulator with a multibit quantizer. Thus a Sigma-Delta ADC usually adds the dynamic element matching digital circuit within feedback loop. It occurs complexity of Sigma-Delta Circuit and increase of power dissipation. In this paper using the Leslie-Singh Structure for improving nonliearity of ADC. This structure operate at low oversampling ratio but is difficult to achieve high resolution. So in this paper propose improving loop filter for single-bit feedback multi-bit quantization Sigma-Delta ADC. It obtained 94.3dB signal to noise ratio over 615kHz bandwidth, and 62mW power dissipation at a sampling frequency of 19.6MHz. This Sigma Delta ADC is fabricated in 0.25um CMOS technology with 2.5V supply voltage.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.1222-1225
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• 2004

This paper presents multibit Sigma-Delta ADC using noise-shaped dynamic element matching(DEM). 5-bit flash ADC for multibit quantization in Sigma Delta modulator offers the following advantages such as lower quantization noise, more accurate white-noise level and more stability over single quantization. For the feedback paths consisting of DAC, the DAC element should have a high matching requirement in order to maintain the linearity performance which can be obtained by the modulator with a multibit quantizer. The DEM algorithm is implemented in such a way as to minimize additional delay within the feedback loop of the modulator Using this algorithm, distortion spectra from DAC linearity errors are shaped. Sigma Delta ADC achieves 82dB signal to noise ratio over 615H7z bandwidth, and 62mW power dissipation at a sampling frequency of 19.6MHz. This Sigma Delta ADC is designed to use 0.25um CMOS technology with 2.5V supply voltage and verified by HSPICE simulation.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1994.06a
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• pp.409-412
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• 1994

• Journal of the Korea Society of Computer and Information
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• v.21 no.5
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• pp.49-56
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• 2016

Increasing Internet traffic and forwarding table size need high performance IP address lookup engine which is a crucial function of routers. For finding the longest matching prefix, trie-based or its variant schemes have been widely researched in software-based IP lookup. As a software router, we enhance the IP address lookup engine using GPU which is a device widely used in high performance applications. We propose a data structure for multibit trie to exploit GPU hardware efficiently. Also, we devise a novel scheme that the root subtrie is loaded on Shared Memory which is specialized for fast access in GPU. Since the root subtrie is accessed on every IP address lookup, its fast access improves the lookup performance. By means of the performance evaluation, our implemented GPU-based lookup engine shows 17~23 times better performance than CPU-based engine. Also, the fast access technique for the root subtrie gives 10% more improvement.