• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.743-744
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• 2006

This paper presents implementation of parallel processing system for image processing. The parallel processing system proposed consisted of 16 processing elements, and multi-access memory system, and interface modules. The multi-access memory system we introduced is made up of a memory module selection, a data routing module, and an address calculation and routing module.

• Journal of IKEEE
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• v.4 no.2 s.7
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• pp.212-224
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• 2000

In this paper, a parallel processing system is proposed for improving the processing speed of image related applications. The proposed parallel processing system is fully synchronous SIMD computer with pipelined architecture and consists of processing elements and a multi-access memory system. The multi-access memory system is made up of memory modules and a memory controller, which consists of memory module selection module, data routing module, and address calculating and routing module, to perform parallel memory accesses with the variety of types: block, horizontal, and vertical access way. Morphological filter had been applied to verify the parallel processing system and resulted in faithful processing speed.

• Journal of Sensor Science and Technology
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• v.26 no.6
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• pp.432-437
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• 2017

As 4.0 industry has been developed, research on a self-driving car technology and related parts of an automobile has been highly investigated recently. Particularly, a TAS(Torque Angle Sensor) module on steering wheel system has been considered as a key technology because of its precise angle, torque detection and high speed signal processing. The environmental assessment is generally required on the TAS module to examine high resolution of angle/torque detection. In the case of existing TAS module, angle detection errors has been occurred by back-lash on main and sub gear in addition to complicated structure caused by gears. In this paper, a structure of the TAS module, which minimizes the numbers of components and angle detection errors on the module compared with the existing TAS module, for vehicle steering system based on a Multi-track Encoder has been proposed. Also, angle detection signal processing board, and key technology of the TAS module were fabricated and evaluated. As a result of the experiments, we confirmed an excellent performance of the fabricated signal processing board for angle detection and an applicability of the fabricated angle detection board on the TAS module of vehicles by the environmental assessment an automobile standard.

• Communications for Statistical Applications and Methods
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• v.19 no.4
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• pp.571-577
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• 2012

Modules that consist of software are respectively coded in the early development phase and the modules are unified as a software. After unification, the software is repeatedly tested with a given taskset (the set of module tasks that are tested simultaneously) until a required performance level is satisfied. In this paper, we expand the one-module software debugging model of Jang and Lee (2011) to a multi-module debugging model and derive the taskset completion probability and the mean of the completed tasksets under the assumption that the processing times of module tasks given in a taskset are mutually dependent.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.429-432
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• 2000

The new MPEG-4 video coding standard enables content-based functionalities. In order to support the philosophy of the MPEG-4 visual standard, each frame of video sequences should be represented in terms of video object planes (VOP’s). In other words, video objects to be encoded in still pictures or video sequences should be prepared before the encoding process starts. Therefore, it requires a prior decomposition of sequences into VOP’s so that each VOP represents a moving object. A parallel processing system is required an automatic segmentation to be processed in real-time, because an automatic segmentation is time consuming. This paper addresses the parallel processing: system for an automatic segmentation for separating moving object from the background in image sequences. The proposed parallel processing system comprises of processing elements (PE’s) and a multi-access memory system (MAMS). Multi-access memory system is a memory controller to perform parallel memory access with the variety of types: horizontal, vertical, and block access way. In order to realize these ways, a multi-access memory system consists of a memory module selection module, data routing modules, and an address calculation and routing module. The proposed system is simulated and evaluated by the CADENCE Verilog-XL hardware simulation package.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.9
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• pp.5652-5659
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• 2014

The purpose of this study was to introduce a software task processing evaluation model that considers the following situations: i) a software system is integratedly composed of several number of modules, ii) each modules has its corresponding module task, iii) all module tasks are tested simultaneously, and iv) the processing times of the module tasks are mutually dependent. The software task completion probability with the module dependency was derived using the joint distribution function of Farlie [11]. The results showed that the task completion probability of software increases with increasing module dependency parameter.

• Journal of Information Processing Systems
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• v.18 no.6
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• pp.794-802
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• 2022

The recovery of reasonable depth information from different scenes is a popular topic in the field of computer vision. For generating depth maps with better details, we present an efficacious monocular depth prediction framework with coordinate attention and feature fusion. Specifically, the proposed framework contains attention, multi-scale and feature fusion modules. The attention module improves features based on coordinate attention to enhance the predicted effect, whereas the multi-scale module integrates useful low- and high-level contextual features with higher resolution. Moreover, we developed a feature fusion module to combine the heterogeneous features to generate high-quality depth outputs. We also designed a hybrid loss function that measures prediction errors from the perspective of depth and scale-invariant gradients, which contribute to preserving rich details. We conducted the experiments on public RGBD datasets, and the evaluation results show that the proposed scheme can considerably enhance the accuracy of depth prediction, achieving 0.051 for log10 and 0.992 for δ<1.25³ on the NYUv2 dataset.

• Proceedings of the Korea Information Processing Society Conference
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• 2022.11a
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• pp.308-310
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• 2022

With the rise of the Al wave, task-oriented dialogue systems have become one of the popular research directions in academia and industry. Currently, task-oriented dialogue systems mainly adopt pipelined form, which mainly includes natural language understanding, dialogue state decision making, dialogue state tracking and natural language generation. However, pipelining is prone to error propagation, so many task-oriented dialogue systems in the market are only for single-round dialogues. Usually single- domain dialogues have relatively accurate semantic understanding, while they tend to perform poorly on multi-domain, multi-round dialogue datasets. To solve these issues, we developed a paddle-based multi-domain task-oriented Chinese dialogue system. It is based on NEZHA-base pre-training model and CrossWOZ dataset, and uses intention recognition module, dichotomous slot recognition module and NER recognition module to do DST and generate replies based on rules. Experiments show that the dialogue system not only makes good use of the context, but also effectively addresses long-term dependencies. In our approach, the DST of dialogue tracking state is improved, and our DST can identify multiple slotted key-value pairs involved in the discourse, which eliminates the need for manual tagging and thus greatly saves manpower.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.4
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• pp.258-264
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• 2015

The first 77 GHz transceiver that applies a heterodyne structure-based linear frequency modulation-frequency shift keying (LFM-FSK) front-end module (FEM) is presented. An LFM-FSK waveform generator is proposed for the transceiver design to avoid ghost target detection in a multi-target environment. This FEM consists of three parts: a frequency synthesizer, a 77 GHz up/down converter, and a baseband block. The purpose of the FEM is to make an appropriate beat frequency, which will be the key to solving problems in the digital signal processor (DSP). This paper mainly focuses on the most challenging tasks, including generating and conveying the correct transmission waveform in the 77 GHz frequency band to the DSP. A synthesizer test confirmed that the developed module for the signal generator of the LFM-FSK can produce an adequate transmission signal. Additionally, a loop back test confirmed that the output frequency of this module works well. This development will contribute to future progress in integrating a radar module for multi-target detection. By using the LFM-FSK waveform method, this radar transceiver is expected to provide multi-target detection, in contrast to the existing method.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.963-971
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• 1990

This paper proposes a memory intensive VLSI architecture for the realization of real-time 3x3 neighborhood processor based on the distributed arithmetic. The proposed architecture is characterized by a bit serial and multi-kernel parallel processing which exploits the pixel kernel parallelism and concurrency. The chip implements 8 neighborhood processing elements in parallel with efficirnt input and output modules which operate concurrently. Besides the a4chitectural design of a neighborhood processor, the design methodology using module generator concept has been considered and MOGOT(MOdule Generator Oriented VLSI design Tool) has been constructed based on the workstation. Based on these design environments MOGOT, it has been shown that the main part of the suggested architecture can be designed efficiently using 2\ulcorner double metal CMOS technology. It includes design of input delay and data conversion module, look-up table for inner product operation, carry save accumulator, output data converter and delay module, and control module.