• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.1
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• pp.49-55
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• 2007

To improved the multi-resolution fast hierarchical motion estimation by using de-interlacing algorithm that is effective in term of both performance and VLSI implementation, is proposed so as to cover large search area field-based as well as frame based image processing in SoC design. In this paper, we have simulated a various picture mode M=2 or M=3. As a results, the proposed algorithm achieved the motion estimation performance PSNR compare with the full search block matching algorithm, the average performance degradation reached to -0.7dB, which did not affect on the subjective quality of reconstructed images at all. And acquiring the more desirable to adopt design SoC for the fast hierarchical motion estimation, we exploit foreground and background search algorithm (FBSA) base on the dual arithmetic processor element(DAPE). It is possible to estimate the large search area motion displacement using a half of number PE in general operation methods. And the proposed architecture of MHME improve the VLSI design hardware through the proposed FBSA structure with DAPE to remove the local memory. The proposed FBSA which use bit array processing in search area can improve structure as like multiple processor array unit(MPAU).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.16-25
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• 2002

This paper presents a methodology and application for extracting parasitic inductances in a multi-level interconnect semiconductor structure by a numerical technique. In order to calculate the parasitic inductances, the distrubution of electric potential and current density in the metal lines are calculated by finite element method (FEM). Thereafter, the magneto-static energy caused by the current density in metal lines was calculated. The result of simulation is compared with the result of Grover equation about analytic simple structures, and 4 bit ROM array with a dimension of $13{\times}10.25{\times}8.25{\mu}m^3$ was simulated to extract the parasitic inductnaces. In this calculation, 6,358 nodes with 31,941 tetrahedra were used in ULTRA 10 workstation. The total CPU time for the simulation was about 150 seconds, while the memory size of 20 MB was required.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.30 no.7
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• pp.144-149
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• 2002

This paper presents a technique for real time multiprocessor parallel processing to develop an avionic system computer(ASC) which integrates the avionics control, navigation and fire control, cursive and raster graphic symbol generation into one line replaceable unit. The proposed method has optimal performance by adopting a logically asymmetric structure between four 32bit RISC processors based on the master-slave multiprocessing, a tightly coupled interaction level with the time shared common bus and global memory, and an efficient bus arbitration algorithm. The ASC has been verified through a series of flight tests. The relevant tests also have been rigorously conducted on the prototype ASC such as electrical test, environmental test, and electromagnetic interference test.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.12C
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• pp.1014-1020
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• 2008

Storage devices such as memories are widely used in various electronic products. They require high-density memory and currently the data has been stored in multi-level format, that results in high error rate. In this paper, we apply error correction schemes that are widely used in communication system to the storage devices for satisfying low bit error rate and high code rate. In A WGN channel with average BER $10^{-5}$ and $5{\times}10^{-6}$, we study error correction schemes for 4-1evel cell to achieve target code rate 0.99 and target BER $10^{-11}$ and $10^{-13}$, respectively. Since block codes may perform better than the concatenated codes for high code rate, and it is important to use less degraded inner code even when many bits are punctured. The performance of concatenated codes using general feedforward systematic convolutional codes are worse than the block code only scheme. The simulation results show that RSC codes must be used as inner codes to achieve good performance of punctured convolutional codes for high code rate.

• The Transactions of the Korea Information Processing Society
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• v.4 no.7
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• pp.1759-1769
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• 1997

The Error BackPropagation (EBP) algorithm for multi-layered neural networks is widely used in various areas such as associative memory, speech recognition, pattern recognition and robotics, etc. Nevertheless, many researchers have continuously published papers about improvements over the original EBP algorithm. The main reason for this research activity is that EBP is exceeding slow when the number of neurons and the size of training set is large. In this study, we developed new learning speed acceleration methods using variable learning rate, variable momentum rate and variable slope for the sigmoid function. During the learning process, these parameters should be adjusted continuously according to the total error of network, and it has been shown that these methods significantly reduced learning time over the original EBP. In order to show the efficiency of the proposed methods, first we have used binary data which are made by random number generator and showed the vast improvements in terms of epoch. Also, we have applied our methods to the binary-valued Monk's data, 4, 5, 6, 7-bit parity checker and real-valued Iris data which are famous benchmark training sets for machine learning.

• Journal of KIISE:Information Networking
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• v.37 no.3
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• pp.175-186
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• 2010

Due to the emergence of new application programs and the fast growth of Internet users, Internet routers are required to provide the quality of services according to the class of input packets, which is identified by wire-speed packet classification. For a pre-defined rule set, by performing multi-dimensional search using various header fields of an input packet, packet classification determines the highest priority rule matching to the input packet. Efficient packet classification algorithms have been widely studied. Tuple pruning algorithm provides fast classification performance using hash-based search against the candidate tuples that may include matching rules. Bloom filter is an efficient data structure composed of a bit vector which represents the membership information of each element included in a given set. It is used as a pre-filter determining whether a specific input is a member of a set or not. This paper proposes new tuple pruning algorithms using Bloom filters, which effectively remove unnecessary tuples which do not include matching rules. Using the database known to be similar to actual rule sets used in Internet routers, simulation results show that the proposed tuple pruning algorithm provides faster packet classification as well as consumes smaller memory amount compared with the previous tuple pruning algorithm.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.4 s.310
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• pp.123-132
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• 2006

In this paper, the digital video and audio system is improved so that various digital video data formats in DVD disc, and digital audio data formats through the S/PDIF ports may be decoded. It is not easy to implement all decoding functions of video and audio by a DVD processor. The special structure in audio decoding circuit is proposed in this system so as to have simultaneously almost same video and audio performance in quality. By dividing the decoding circuit separately into video and audio part, the audio quality can be dramatically improved together with supporting several audio formats and with several effects. In order to satisfy the perfect audio system to support to audio decoding formats, it is just enough to get the expensive, complicated decoder. However, it may be not easy to get this expensive decoder in near future. Therefore it is rather to adopt the downloading method by which the host should download the appropriate code into memory by detecting the corresponding audio bit streams. It is proved that this method may be efficient in the point of sharing resource of audio data for video decoding.