• 대한전기학회논문지:전력기술부문A
• /
• 제50권2호
• /
• pp.83-89
• /
• 2001

This paper introduces a power flow model of SSSC for voltage stability analysis of power system installed with Static Synchronous Compensators. The SSSC model is obtained from the injection model of voltage source inverter by adding the condition that SSSC injection voltage is in quadrature with current of SSSC-installed branch. This model is incorporated into modified CPF algorithm to study effects of SSSC on the security-constrained interface flow limit. Determination of interface flow limit is simply briefed. In case study a 771-bus real system is used to show that interface flow limit can be improved by appropriate control of SSSC in terms of voltage stability.

• Journal of Microbiology and Biotechnology
• /
• 제31권7호
• /
• pp.903-911
• /
• 2021

Previous studies have modified microbial genomes by introducing gene cassettes containing selectable markers and homologous DNA fragments. However, this requires several steps including homologous recombination and excision of unnecessary DNA regions, such as selectable markers from the modified genome. Further, genomic manipulation often leaves scars and traces that interfere with downstream iterative genome engineering. A decade ago, the CRISPR/Cas system (also known as the bacterial adaptive immune system) revolutionized genome editing technology. Among the various CRISPR nucleases of numerous bacteria and archaea, the Cas9 and Cas12a (Cpf1) systems have been largely adopted for genome editing in all living organisms due to their simplicity, as they consist of a single polypeptide nuclease with a target-recognizing RNA. However, accurate and fine-tuned genome editing remains challenging due to mismatch tolerance and protospacer adjacent motif (PAM)-dependent target recognition. Therefore, this review describes how to overcome the aforementioned hurdles, which especially affect genome editing in higher organisms. Additionally, the biological significance of CRISPR-mediated microbial genome editing is discussed, and future research and development directions are also proposed.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2000년도 하계학술대회 논문집 A
• /
• pp.28-30
• /
• 2000

This paper introduces a power flow model of SSSC for voltage stability study. The SSSC model is obtained from the injection model of voltage source inverter by adding the condition that SSSC injection voltage is in quadrature with current of SSSC-installed branch. This model is incorporated into modified CPF algorithm to study effects of SSSC on the security-constrained interface flow limit. Determination of interface flow limit is simply briefed. In case study a 771-bus real system is used to show that SSSC can improve interface flow limit in terms of voltage stability.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1999년도 하계학술대회 논문집 C
• /
• pp.1514-1516
• /
• 1999

This paper presents a sequential framework that calculates the total transfer capabilities of power transmission systems. The proposed algorithm enhances the Power System Transfer Capability Program (PSTCP) in conjunction with the Continuation Power Flow(CPF) that is used for steady-state voltage stability analysis and modified Arnoldi-Chebyshev method that calculates rightmost eigenvalues for small signal stability analysis. The proposed algorithm is applied to IEEE 39-bus test system to calculate TTC.

• 한국콘크리트학회:학술대회논문집
• /
• 한국콘크리트학회 1998년도 가을 학술발표대회 논문집(III)
• /
• pp.603-608
• /
• 1998

This study was performed to examine the effect of time dependent properties on RC columns in subway structures subjected to high filled soil layer. By using Program TCC which is a modified version of CPF for the present purpose, a typical column in subway structure was analyzed. Four different model equations for predicted time dependent concrete properties(ACI, CEB-FIP, Bazant & Panula and Korea Bridge Specification) was employed, and the results were compared. It was found that a relevant creep coefficient is recommended to be 1.0 for designing columns in subway structure, and the sol filling work would be performed at least 3 months later after the concrete casting in order to ensure durability by reducing the negative effect of concrete time dependent properties.

• 대한전자공학회논문지SD
• /
• 제37권5호
• /
• pp.55-65
• /
• 2000

본 논문에서는 CPF(Carry-Propagation-Free)의 특성을 갖는 RB(Redundant Binary)연산을 이용한 새로운 구조의 24비트 2의 보수 덧셈기를 설계하였다. TC2RB(Two's Complement to RB SUM converter)의 속도와 트랜지스터 개수를 줄이기 위해 MPPL(Modifed PPL) XOR/XNOR 게이트를 제안하고 고속 RB2TC(RB SUM to Two's Complement converter)를 사용한 두 가지 형태의 덧셈기를 제안하였다. 각 덧셈기의 특징을 살펴보면, TYPE 1 덧셈기는 VGS(Variable Group Select) 방식을 사용하여 덧셈기의 속도를 향상시켰으며 TYPE 2 덧셈기는 64비트 GCG(Group Change bit Generator)회로와 8비트 TYPE 1 덧셈기를 사용하여 속도를 향상시켰다. 64비트 TYPE 1 덧셈기의 경우 CLA와 CSA에 비해 각각 23.5%, 29.7%의 속도 향상을 TYPE 2 덧셈기의 경우 각각 41.2%, 45.9%의 속도 향상을 기대할 수 있다. 레이아웃된 24비트 TYPE 1과 TYPE 2 덧셈기의 전달지연 시간은 각각 1.4ns와 1.2ns로 나왔다. 제안한 덧셈기는 매우 규칙적인 구조를 가지고 있기 때문에 빠른 시간에 회로 설계 및 레이아웃이 가능하며 마이크로프로세서나 DSP 등과 같이 고속연산을 필요로 하는 경우에 적합하다.