• The Transactions of the Korean Institute of Electrical Engineers A
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• v.50 no.2
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• pp.83-89
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• 2001

This paper introduces a power flow model of SSSC for voltage stability analysis of power system installed with Static Synchronous Compensators. The SSSC model is obtained from the injection model of voltage source inverter by adding the condition that SSSC injection voltage is in quadrature with current of SSSC-installed branch. This model is incorporated into modified CPF algorithm to study effects of SSSC on the security-constrained interface flow limit. Determination of interface flow limit is simply briefed. In case study a 771-bus real system is used to show that interface flow limit can be improved by appropriate control of SSSC in terms of voltage stability.

• Journal of Microbiology and Biotechnology
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• v.31 no.7
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• pp.903-911
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• 2021

Previous studies have modified microbial genomes by introducing gene cassettes containing selectable markers and homologous DNA fragments. However, this requires several steps including homologous recombination and excision of unnecessary DNA regions, such as selectable markers from the modified genome. Further, genomic manipulation often leaves scars and traces that interfere with downstream iterative genome engineering. A decade ago, the CRISPR/Cas system (also known as the bacterial adaptive immune system) revolutionized genome editing technology. Among the various CRISPR nucleases of numerous bacteria and archaea, the Cas9 and Cas12a (Cpf1) systems have been largely adopted for genome editing in all living organisms due to their simplicity, as they consist of a single polypeptide nuclease with a target-recognizing RNA. However, accurate and fine-tuned genome editing remains challenging due to mismatch tolerance and protospacer adjacent motif (PAM)-dependent target recognition. Therefore, this review describes how to overcome the aforementioned hurdles, which especially affect genome editing in higher organisms. Additionally, the biological significance of CRISPR-mediated microbial genome editing is discussed, and future research and development directions are also proposed.

• Proceedings of the KIEE Conference
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• 2000.07a
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• pp.28-30
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• 2000

This paper introduces a power flow model of SSSC for voltage stability study. The SSSC model is obtained from the injection model of voltage source inverter by adding the condition that SSSC injection voltage is in quadrature with current of SSSC-installed branch. This model is incorporated into modified CPF algorithm to study effects of SSSC on the security-constrained interface flow limit. Determination of interface flow limit is simply briefed. In case study a 771-bus real system is used to show that SSSC can improve interface flow limit in terms of voltage stability.

• Proceedings of the KIEE Conference
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• 1999.07c
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• pp.1514-1516
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• 1999

This paper presents a sequential framework that calculates the total transfer capabilities of power transmission systems. The proposed algorithm enhances the Power System Transfer Capability Program (PSTCP) in conjunction with the Continuation Power Flow(CPF) that is used for steady-state voltage stability analysis and modified Arnoldi-Chebyshev method that calculates rightmost eigenvalues for small signal stability analysis. The proposed algorithm is applied to IEEE 39-bus test system to calculate TTC.

• Proceedings of the Korea Concrete Institute Conference
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• 1998.10b
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• pp.603-608
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• 1998

This study was performed to examine the effect of time dependent properties on RC columns in subway structures subjected to high filled soil layer. By using Program TCC which is a modified version of CPF for the present purpose, a typical column in subway structure was analyzed. Four different model equations for predicted time dependent concrete properties(ACI, CEB-FIP, Bazant & Panula and Korea Bridge Specification) was employed, and the results were compared. It was found that a relevant creep coefficient is recommended to be 1.0 for designing columns in subway structure, and the sol filling work would be performed at least 3 months later after the concrete casting in order to ensure durability by reducing the negative effect of concrete time dependent properties.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.5
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• pp.55-65
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• 2000

In this paper a new architecture of 24-bit two's complement adder is designed by using RB(Redundant Binary) arithmetic which has the advantage of CPF(Carry-Propagation-Free). A MPPL(Modified PPL) XOR/XNOR gate is applied to improve a TC2RB(Two's Complement to RB SUM converter) speed and to reduce the number of transistors, and we proposed two types adder which used a fast RB2TC(RB SUM to Two's Complement converter). The property of two types adder is followings. The improvement of TYPE 1 adder speed is archived through the use of VGS(Variable Group Select) method and TYPE 2 adder is through the use of a 64-bit GCG(Group Change bit Generator) circuit and a 8-bit TYPE 1 adder. For 64-bit, TYPE 1 adder can be expected speed improvement of 23.5%, 25.7% comparing with the CLA and CSA, and TYPE 2 adder can be expected 41.2%, 45.9% respectively. The propagation delay of designed 24-bit TYPE 1 adder is 1.4ns and TYPE 2 adder is 1.2ns. The implementation is highly regular with repeated modules and is very well suited for microprocessor systems and fast DSP units.