• 한국통신학회논문지
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• 제25권10B호
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• pp.1648-1664
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• 2000

This paper proposes a real-time dynamic storage allocation algorithm QSHF(quick-segregated-half-fit) that provides various memory allocation policies. that manages a free block list per each word size for memory requests of small size good(segregated)-fit policy that manages a free list per proper range size for medium size requests and half-fit policy that manages a free list per proper range size for medium size requests and half-fit policy that manages a free list per each power of 2 size for large size requests. The proposed algorithm has the time complexit O(1) and makes us able to easily estimate the worst case execution time(WCET). This paper also suggests two algorithm that finds the proper free list for the requested memory size in predictable time and if the found list is empty then finds next available non-empty free list in fixed time. In order to confirm efficiency of the proposed algorithm we simulated the memory utilization of each memory allocation policy. The simulation result showed that each policy guarantees the constant WCET regardless of memory size but they have trade-off between memory utilization and list management overhead.

• ETRI Journal
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• 제26권6호
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• pp.615-621
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• 2004

Next generation mobile communication system, such as IMT-2000, adopts Turbo codes due to their powerful error correction capability. This paper presents a block-wise maximum a posteriori (MAP) Turbo decoding structure with a low memory requirement. During this research, it has been observed that the training size and block size determine the amount of required memory and bit-error rate (BER) performance of the block-wise MAP decoder, and that comparable BER performance can be obtained with much shorter blocks when the training size is sufficient. Based on this observation, a new decoding structure is proposed and presented in this paper. The proposed block-wise decoder employs a decoding scheme for reducing the memory requirement by setting the training size to be N times the block size. The memory requirement for storing the branch and state metrics can be reduced 30% to 45%, and synthesis results show that the overall memory area can be reduced by 5.27% to 7.29%, when compared to previous MAP decoders. The decoder throughput can be maintained in the proposed scheme without degrading the BER performance.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제8권6호
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• pp.2139-2151
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• 2014

Embedded system testing, especially long-term reliability testing, of flash memory solutions such as embedded multi-media card, secure digital card and solid-state drive involves strategic decision making related to test sample size to achieve high test coverage. The test sample size is the number of flash memory devices used in a test. Earlier, there were physical limitations on the testing period and the number of test devices that could be used. Hence, decisions regarding the sample size depended on the experience of human testers owing to the absence of well-defined standards. Moreover, a lack of understanding of the importance of the sample size resulted in field defects due to unexpected user scenarios. In worst cases, users finally detected these defects after several years. In this paper, we propose that a large number of potential field defects can be detected if an adequately large test sample size is used to target weak features during long-term reliability testing of flash memory solutions. In general, a larger test sample size yields better results. However, owing to the limited availability of physical resources, there is a limit on the test sample size that can be used. In this paper, we address this problem by proposing a self-adaptive reliability testing scheme to decide the sample size for effective long-term reliability testing.

• 열처리공학회지
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• 제3권1호
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• pp.34-41
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• 1990

Effects of grain size and cold rolling degree on shape memory ability and transformation temperature were studied in Fe-35% Mn-6% Si shape memory alloy. Md point of the alloy was determined by variation of yield stress with test temperature. The Md point measured in this way was linearly increased with increasing grain size. Shape memory ability of the alloy was decreased with increasing grain size, showing a minimum value at around $63{\mu}m$, and then increased with increasing grain size. From this result, it was concluded that the shape memory ability in the grain size smaller than a critical value is controlled by amount of retained ${\gamma}$ and prior ${\varepsilon}$ phase, but that the shape memory ability in the grain size greater than the critical value is mainly dominated by grain boundary area in unit volume of parent phase. The shape memory ability was decreased with increasing deformation degree. This was because the ${\gamma}$ content being available for the formation of ${\varepsilon}$ martensite during bending was decreased with increasing deformation degree.

• 한국컴퓨터정보학회논문지
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• 제21권4호
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• pp.1-8
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• 2016

In small embedded systems including IoT devices, memory size is very small and it is important to reduce memory amount for execution of application programs. For multi-threaded applications, stack may consume a large amount of memory because each thread has its own stack of sufficiently large size for worst case. This paper presents an implementation of single stack multi-threading, called SSThread (Single Stack Thread), by sharing a stack for all threads to reduce stack memory size. By using SSThread, multi-threaded applications can be programmed based on normal C language environment and there is no requirement of transporting multi-threading operating systems. It consists of several library functions and various C macro definitions. Even though some functional restrictions in comparison to operating systems supporting complete multi-thread functionalities, it is very useful for small embedded systems with tiny memory size and it is simple to setup programming environment for multi-thread applications.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 Ⅲ
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• pp.1335-1338
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• 2003

Fixed-size memory allocation is one of the most promising way to avoid external fragmentation in dynamic memory allocation problem. This paper presents an experimental result of applying the fixed- size memory allocation strategy to Java virtual machine for embedded system. The result says that although this strategy induces another memory utilization problem caused by internal fragmentation, the effect is not very considerable and this strategy is well-suited for embedded Java system. The experiment has been performed in a real embedded Java system called the simpleRTJ.

• 한국컴퓨터정보학회논문지
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• 제22권9호
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• pp.1-8
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• 2017

In this paper, we propose a file system for flash memory which remedies shortcomings of existing flash memory file systems. Besides supporting large block size, the proposed file system reduces time in initializing file system significantly by adopting logical address comprised of erase block number and bitmap for pages in the block to find a page. The file system is suitable for embedded systems with limited main memory since it has small in-memory data structures. It also provides efficient management of obsolete blocks and free blocks, which contribute to the reduction of file update time. Finally the proposed file system can easily configure the maximum file size and file system size limits, which results in portability to emerging larger flash memories. By conducting performance evaluation studies, we show that the proposed file system can contribute to the performance improvement of embedded systems.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2003년도 추계종합학술대회
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• pp.548-551
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• 2003

JSize 는 유닉스 운영체제의 size 프로그램에 대응하는 자바 등가 프로그램이다. 유닉스 size 프로그램은 실행 파일을 분석하여 그 파일이 메모리에 적재되었을 때 얼마 정도의 코드와 데이터 영역을 차지할지를 예측하게 한다. 마찬가지로 JSize 는 자바 클래스 파일을 분석하여 그 파일이 메모리에 적재되었을 때 얼마 정도의 클래스 영역 메모리를 차지할지를 예측하게 하는 기능을 갖는다. 본 논문은 클래스 파일을 분석하여 얻은 정보로부터 클래스 영역의 크기를 예측할 수 있게 하는 원리에 대해 소개한다. 아울러 실험을 통해 JSize 의 예측 정확성을 실제로 알아보았다.

• International Journal of Internet, Broadcasting and Communication
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• 제10권4호
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• pp.6-11
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• 2018

As embedded memory technology evolves, the traditional Static Random Access Memory (SRAM) technology has reached the end of development. For deepening the manufacturing process technology, the next generation memory technology is highly required because of the exponentially increasing leakage current of SRAM. Non-volatile memories such as STT-MRAM (Spin Torque Transfer Magnetic Random Access Memory), PCM (Phase Change Memory) are good candidates for replacing SRAM technology in embedded memory systems. They have many advanced characteristics in the perspective of power consumption, leakage power, size (density) and latency. Nonetheless, nonvolatile memories have two major problems that hinder their use it the next-generation memory. First, the lifetime of the nonvolatile memory cell is limited by the number of write operations. Next, the write operation consumes more latency and power than the same size of the read operation.These disadvantages can be solved using the compiler. The disadvantage of non-volatile memory is in write operations. Therefore, when the compiler decides the layout of the data, it is solved by optimizing the write operation to allocate a lot of data to the SRAM. This study provides insights into how these compiler and architectural designs can be developed.

• 한국정보처리학회논문지
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• 제7권7호
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• pp.2204-2218
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• 2000

This paper proposes a dynamic storage allocation algorithm, QHF(quick-half-fit) for real-time systems. The proposed algorithm manages a free block list per each worked size for memory requests of small size, and a free block list per each power of 2 size for memory requests of large size. This algorithms uses the exact-fit policy for small sie requests and provides high memory utilization. The proposed algorithm also has the time complexity O(I) and enables us to easily estimate the worst case execution time (WCET). In order to confirm efficiency of the proposed algorithm, we compare he memory utilization of proposed algorithm with that of half-fit and binary buddy system that have also time complexity O(I). The simulation result shows that the proposed algorithm guarantees the constant WCET regardless of the system memory size and provides lower fragmentation ratio and allocation failure ratio thant other two algorithms.