• Journal of the Korean Ceramic Society
• /
• v.38 no.9
• /
• pp.782-786
• /
• 2001

Cobalt silicide has been employed to Embedded DRAM (Dynamic Random Access Memory) and Logic (EDL) as contact material to improve its speed. We have investigated the influences of Ti and TiN capping layers on cobalt-silicided Complementary Metal-Oxide-Semiconductor (CMOS) device characteristics. TiN capping layer is shown to be superior to Ti capping layer with respect to high thermal stability and the current driving capability of pMOSFETs. Secondary Ion Mass Spectrometry (SIMS) showed that the Ti capping layer could not prevent the out-diffusion of boron dopants. The resulting operating current of MOS devices with Ti capping layer was degraded by more than 10%, compared with those with TiN.

• Transactions on Electrical and Electronic Materials
• /
• v.12 no.1
• /
• pp.16-19
• /
• 2011

The oxide-nitride-oxide (ONO) deposition process was added to the beginning of a 0.25 ${\mu}m$ embedded polysiliconoxide-nitride-oxide-silicon (SONOS) process before all of the logic well implantation processes in order to maintain the characteristics of basic CMOS(complementary metal-oxide semiconductor) logic technology. The system subsequently suffered severe ONO rupture failure. The damage was caused by the ONO implantation and was responsible for the ONO rupture failure in the embedded SONOS process. Furthermore, based on the experimental results as well as an implanted ion's energy loss model, processes primarily producing permanent displacement damages responsible for the ONO rupture failure were investigated for the embedded SONOS process.

• Journal of the Semiconductor & Display Technology
• /
• v.5 no.4 s.17
• /
• pp.17-22
• /
• 2006

In the manufacturing processes of semiconductor, test process is important for quality of products. In the manufacturing process of dynamic memory, memory test is more important. So, automatic test equipment(ATE) is used necessarily. But, according to increase of speed of dynamic memory operation, the rapid test equipment is needed. Impedance matching between ATE and dynamic memory is expected to be an important problem for making a rapid test equipment over 1Gbps. According to increase of speed, inner impedance of ATE also works on important parameter for test. This paper is about the method that is for impedance matching of inner impedance and coaxial cable occurring in manufacturing of ATE. We proved effects of inner impedance by electric theory and verified the method of impedance matching using computer simulation.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.12 no.4
• /
• pp.449-457
• /
• 2012

The program/erase (P/E) cyclic endurances including bias temperature instability (BTI) behaviors of Metal-$Al_2O_3$-Nitride-Oxide-Semiconductor (MANOS) memories are investigated in comparison with those of Semiconductor-Oxide-Nitride-Oxide-Semiconductor (SONOS) memories. In terms of BTI behaviors, the SONOS power-law exponent n is ~0.3 independent of the P/E cycle and the temperature in the case of programmed cell, and 0.36~0.66 sensitive to the temperature in case of erased cell. Physical mechanisms are observed with thermally activated $h^*$ diffusion-induced Si/$SiO_2$ interface trap ($N_{IT}$) curing and Poole-Frenkel emission of holes trapped in border trap in the bottom oxide ($N_{OT}$). In terms of the BTI behavior in MANOS memory cells, the power-law exponent is n=0.4~0.9 in the programmed cell and n=0.65~1.2 in the erased cell, which means that the power law is strong function of the number of P/E cycles, not of the temperature. Related mechanism is can be explained by the competition between the cycle-induced degradation of P/E efficiency and the temperature-controlled $h^*$ diffusion followed by $N_{IT}$ passivation.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
• /
• 2006.05a
• /
• pp.21-40
• /
• 2006

[ ${\Box}$ ] Opportunities for PRAM Nearly ideal memory characteristics Potential for high density & low cost memory ${\Box}$ Technical Challenges Writing current reduction is the most urgent issue. ${\to}$ chalcogenide, programming volume, current density, heat loss control Improvement of writing speed, reliability ${\Box}$ Prospects (PRAM as a Mainstream Memory) Evenn, We have demonstrated 256Mb PRAM Realization of high density and low cost PRAM with good reliability will be key succss factor. We need to develop PRAM specific applications.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.6 no.2
• /
• pp.87-89
• /
• 2006

This paper proposes a sense amplifier with non-volatile memory in order to improve the image quality of LCD by enhancing the matching of the driving voltages between the panel and driver. The sense amplifier having a wide sensing margin and fast response adjusts LCD driver voltage of display driver. The CSTN-LCD with the sense amplifier results improved image quality than that with conventional 6 bit column driver without it.

• KDI Journal of Economic Policy
• /
• v.46 no.3
• /
• pp.1-23
• /
• 2024

This study empirically investigates the impact of recent US export controls on China on South Korea's semiconductor exports. We analyze South Korean export data to shed light on the repercussions of US export restrictions on a third country. Our findings reveal a significant decline in Korean semiconductor exports following the October 2022 imposition of US controls. This decline was most pronounced in the memory, discrete devices, and discrete device components subsectors of the semiconductor industry. In addition, we observed a decrease in unit prices, especially for memory semiconductors, pointing to downward pressure on South Korea's high-value-added semiconductor exports. These results provide some evidence of substantial negative impacts of US export controls on South Korea's semiconductor industry, and particularly with regard to its high-tech products.

• Journal of the Semiconductor & Display Technology
• /
• v.5 no.1 s.14
• /
• pp.17-20
• /
• 2006

This paper presents of a new type of memory cell that could potentially replace both DRAM and flash memory. The proposed device cell operates by sensing the state of about 1,000 electrons trapped between unique insulating barriers in the channel region of the upper transistor. These electrons are controlled by a side gate on the transistor, and their state in turn controls the gate of the larger transistor, providing signal gain within the memory cell. It becomes faster and more reliable memory with lower operation voltage. Moreover, the use of a multiple tunnel junction (MTJ) fur the vertical transistor can significantly improve the data retention and operation speed.

• Journal of the Semiconductor & Display Technology
• /
• v.19 no.3
• /
• pp.61-67
• /
• 2020

This paper is to propose a hybrid memory adaptor using next-generation nonvolatile memory devices such as phase-change memory to improve the performance limitations of OpenStack-based object storage systems. The proposed system aims to improve the performance of the account and container servers for object metadata management. For this, the proposed system consists of locality-based dynamic page buffer, write buffer, and nonvolatile memory modules. Experimental results show that the proposed system improves the hit rate by 5.5% compared to the conventional system.

• Journal of the Semiconductor & Display Technology
• /
• v.9 no.2
• /
• pp.67-72
• /
• 2010

Recently increasing application of flash memory in mobile and ubiquitous related devices is due to its non-volatility, fast response time, shock resistance and low power consumption. Following this trend, SSD(Solid State Disk) using multiple flash chips, instead of hard-drive based storage system, started to widely used for its advantageous features. However, flash memory based storage subsystem should resolve the performance bottleneck for writing in perspective of speed and lifetime according to its disadvantageous physical property. In order to provide tangible performance, solutions are studied in aspect of reclaiming of invalid regions by decreasing the number of erasures and distributing the erasures uniformly over the whole memory space as much as possible. In this paper, we study flash memory recycling algorithms with multiple management units and demonstrate that the proposed algorithm provides feasible performance. The proposed method utilizes the partitions of the memory space by utilizing threshold values and reconfigures the management units if necessary. The performance of the proposed policies is evaluated through a number of simulation based experiments.