• 제목/요약/키워드: memory semiconductor

검색결과 575건 처리시간 0.026초

자기진단 기능을 이용한 비동기용 불휘발성 메모리 모듈의 설계 (Design of Asynchronous Nonvolatile Memory Module using Self-diagnosis Function)

  • 신우현;양오;연준상
    • 반도체디스플레이기술학회지
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    • 제21권1호
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    • pp.85-90
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    • 2022
  • In this paper, an asynchronous nonvolatile memory module using a self-diagnosis function was designed. For the system to work, a lot of data must be input/output, and memory that can be stored is required. The volatile memory is fast, but data is erased without power, and the nonvolatile memory is slow, but data can be stored semi-permanently without power. The non-volatile static random-access memory is designed to solve these memory problems. However, the non-volatile static random-access memory is weak external noise or electrical shock, data can be some error. To solve these data errors, self-diagnosis algorithms were applied to non-volatile static random-access memory using error correction code, cyclic redundancy check 32 and data check sum to increase the reliability and accuracy of data retention. In addition, the possibility of application to an asynchronous non-volatile storage system requiring reliability was suggested.

고분해능 전자현미경법을 이용한 (Bi, La)4Ti3O12 박막의 결정학적 특성 평가 (Crystallographic Characterization of the (Bi, La)4Ti3O12 Film by High-Resolution Electron Microscopy)

  • 이덕원;양준모;박태수;김남경;염승진;박주철;이순영;박성욱
    • 한국재료학회지
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    • 제13권7호
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    • pp.478-483
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    • 2003
  • The crystallographic characteristics of the $(Bi, La)_4$$Ti_3$$O_{12}$ thin film, which is considered as an applicable dielectrics in the ferroelectric RAM device due to a low crystallization temperature and a good fatigue property, were investigated at the atomic scale by high resolution transmission electron microscopy and the high resolution Z-contrast technique. The analysis showed that a (00c) preferred orientation and a crystallization of the film were enhanced with the diffraction intensity increase of the (006) and (008) plane as the annealing temperature increased. It indicated a change of the atomic arrangement in the (00c) plane. Stacking faults on the (00c) plane were also observed. Through the comparison of the high-resolution Z-contrast image and the $Bi_4$$Ti_3$$O_{12}$ atomic model, it was evaluated that the intensity of the Bi atom was different according to the atomic plane, and it was attributed to a substitution of La atom for Bi at the specific atom position.

Particle 입자에 의한 CMP 마이크로 스크래치 발생 규명 (Particle induced micro-scratch in CMP process)

  • 황응림;김형환;이훈;피승호;최봉호
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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    • pp.40-41
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    • 2005
  • In this study, we proposed CMP micro-scratches generated by contaminative particle which existed on the wafer surface prior to CMP process. The CMP micro-scratches are one of the slurry abrasive related damage. To reduce the micro-scratches, research efforts have been devoted to the optimization of slurry abrasive size distribution. In addition of slurry abrasive, it was found that contaminative particles also were major CMP micro-scratch source.

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High Quality Vertical Silicon Channel by Laser-Induced Epitaxial Growth for Nanoscale Memory Integration

  • Son, Yong-Hoon;Baik, Seung Jae;Kang, Myounggon;Hwang, Kihyun;Yoon, Euijoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제14권2호
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    • pp.169-174
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    • 2014
  • As a versatile processing method for nanoscale memory integration, laser-induced epitaxial growth is proposed for the fabrication of vertical Si channel (VSC) transistor. The fabricated VSC transistor with 80 nm gate length and 130 nm pillar diameter exhibited field effect mobility of $300cm^2/Vs$, which guarantees "device quality". In addition, we have shown that this VSC transistor provides memory operations with a memory window of 700 mV, and moreover, the memory window further increases by employing charge trap dielectrics in our VSC transistor. Our proposed processing method and device structure would provide a promising route for the further scaling of state-of-the-art memory technology.

Recent Advance of Flexible Organic Memory Device

  • Kim, Jaeyong;Hung, Tran Quang;Kim, Choongik
    • Journal of Semiconductor Engineering
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    • 제1권1호
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    • pp.38-45
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    • 2020
  • With the recent emergence of foldable electronic devices, interest in flexible organic memory is significantly growing. There are three types of flexible organic memory that have been researched so far: floating-gate (FG) memory, ferroelectric field-effect-transistor (FeFET) memory, and resistive memory. Herein, performance parameters and operation mechanisms of each type of memory device are introduced, along with a brief summarization of recent research progress in flexible organic memory.

A Subthreshold Slope and Low-frequency Noise Characteristics in Charge Trap Flash Memories with Gate-All-Around and Planar Structure

  • Lee, Myoung-Sun;Joe, Sung-Min;Yun, Jang-Gn;Shin, Hyung-Cheol;Park, Byung-Gook;Park, Sang-Sik;Lee, Jong-Ho
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제12권3호
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    • pp.360-369
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    • 2012
  • The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NAND flash memory with planar structure were investigated. To analyze the difference in SSs, TCAD simulation and low-frequency noise (LFN) measurement were fulfilled. The device simulation was performed to compare SSs considering the gate electric field effect to the channel and to check the localized trapped charge distribution effect in nitride layer while the comparison of noise power spectrum was carried out to inspect the generation of interface traps ($N_{IT}$). When each cell in the measured two memory devices is erased, the normalized LFN power is increased by one order of magnitude, which is attributed to the generation of $N_{IT}$ originated by the movement of hydrogen species ($h^*$) from the interface. As a result, the SS is degraded for the GAA SONOS memory device when erased where the $N_{IT}$ generation is a prominent factor. However, the TANOS memory cell is relatively immune to the SS degradation effect induced by the generated $N_{IT}$.

자기진단과 시계 기능을 갖는 비동기용 불휘발성 메모리 모듈의 설계 (Design of Asynchronous Nonvolatile Memory Module with Self-diagnosis and Clock Function)

  • 신우현;이강원;양오
    • 반도체디스플레이기술학회지
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    • 제22권1호
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    • pp.43-48
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    • 2023
  • This paper discusses the design of 32Mbyte asynchronous nonvolatile memory modules, which includes self-diagnosis and RTC (Real Time Clock) functions to enhance their data stability and reliability. Nonvolatile memory modules can maintain data even in a power-off state, thereby improving the stability and reliability of a system or device. However, due to the possibility of data error due to electrical or physical reasons, additional data loss prevention methods are required. To minimize data error in asynchronous nonvolatile memory modules, this paper proposes the use of voltage monitoring circuits, self-diagnosis, BBT (Bad Block Table), ECC (Error Correction Code), CRC (Cyclic Redundancy Check)32, and data check sum, data recording method using RTC. Prototypes have been produced to confirm correct operation and suggest the possibility of commercialization.

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낸드 플래시 메모리와 PSRAM을 이용한 비동기용 불휘발성 메모리 모듈 설계 (Design of Asynchronous Non-Volatile Memory Module Using NAND Flash Memory and PSRAM)

  • 김태현;양오;연준상
    • 반도체디스플레이기술학회지
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    • 제19권3호
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    • pp.118-123
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    • 2020
  • In this paper, the design method of asynchronous nonvolatile memory module that can efficiently process and store large amounts of data without loss when the power turned off is proposed and implemented. PSRAM, which takes advantage of DRAM and SRAM, was used for data processing, and NAND flash memory was used for data storage and backup. The problem of a lot of signal interference due to the characteristics of memory devices was solved through PCB design using high-density integration technology. In addition, a boost circuit using the super capacitor of 0.47F was designed to supply sufficient power to the system during the time to back up data when the power is off. As a result, an asynchronous nonvolatile memory module was designed and implemented that guarantees reliability and stability and can semi-permanently store data for about 10 years. The proposed method solved the problem of frequent data loss in industrial sites and presented the possibility of commercialization by providing convenience to users and managers.

PLC와 CF 메모리를 이용한 FAT32 파일시스템 구현 (Implementation of the FAT32 File System using PLC and CF Memory)

  • 김명균;양오;정원섭
    • 반도체디스플레이기술학회지
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    • 제11권2호
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    • pp.85-91
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    • 2012
  • In this paper, the large data processing and suitable FAT32 file system for industrial system using a PLC and CF memory was implemented. Most of PLC can't save the large data in user data memory. So it's required to the external devices of CF memory or NAND flash memory. The CF memory is used in order to save the large data of PLC system. The file system using the CF memory is NTFS, FAT, and FAT32 system to configure in various ways. Typically, the file system which is widely used in industrial data storage has been implemented as modified FAT32. The conventional FAT 32 file system was not possible for multiple writing and high speed data accessing. The proposed file system was implemented by the large data processing module can be handled that the files are copied at the 40 bytes for 1msec speed logging and creating 8 files at the same time. In a sudden power failure, high reliability was obtained that the problem was solved using a power fail monitor and the non-volatile random-access memory (NVSRAM). The implemented large data processing system was applied the modified file system as FAT32 and the good performance and high reliability was showed.

Rust 언어 메모리 안전 모델에서 스마트 포인터의 역할에 대한 연구 (Understanding The Role of Smart Pointers in the Rust Memory)

  • 카욘도마틴;방인영;백윤흥
    • 한국정보처리학회:학술대회논문집
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    • 한국정보처리학회 2023년도 춘계학술발표대회
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    • pp.345-347
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    • 2023
  • Rust has gained popularity as a memory safe systems programming language. At the center of its memory safety is a strict memory ownership model with stringent rules enforced by the compiler. This paper aims to shed light on this memory safety model and the role smart pointers play towards its success. We study specific smart pointers, their purposes and contribution to Rust's memory safety. We further explore weaknesses of these smart pointers and their APIs, and provide scenarios under which they may lead to memory vulnerabilities in Rust programs.