• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.34-39
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• 2014

This paper discusses the 3-level charge pumping (CP) method in planar-type Silicon-Oxide-High-k-Oxide-Silicon (SOHOS) and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) devices to find out the reason of the degradation of data retention properties. In the CP technique, pulses are applied to the gate of the MOSFET which alternately fill the traps with electrons and holes, thereby causing a recombination current Icp to flow in the substrate. The 3-level charge pumping method may be used to determine not only interface trap densities but also capture cross sections as a function of trap energy. By applying this method, SOHOS device found to have a higher interface trap density than SONOS device. Therefore, degradation of data retention characteristics is attributed to the many interface trap sites.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.53-53
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• 2009

Charge trap flash memory devices with modified tunneling barriers were fabricated using the tunneling barrier engineering technique. Variable oxide thickness (VARIOT) barrier and CRESTED barrier consisting of thin $SiO_2$ and $Si_3N_4$ dielectric layers were used as engineered tunneling barriers. The VARIOT type tunneling barrier composed of oxide-nitride-oxide (ONO) layers revealed reliable electrical characteristics; long retention time and superior endurance. On the other hand, the CRESTED tunneling barrier composed of nitride-oxide-nitride (NON) layers showed degraded retention and endurance characteristics. It is found that the degradation of NON barrier is associated with the increase of interface state density at tunneling barrier/silicon channel by programming and erasing (P/E) stress.

• Transactions on Electrical and Electronic Materials
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• 제16권5호
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• pp.290-292
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• 2015

We have reported about bipolar resistive switching effect on Poly[2-methoxy-5-(2-ethylhexyloxy)-1,4-phenylenevinylene]:Graphene oxide composite films, which are sandwiched between aluminum and indium tin oxide electrodes. In this case, I-V sweep curve showed a hysteretic behavior, which varied according to the polarity of the applied voltage bias. The device exhibited excellent switching characteristics, with the ON/OFF ratio being approximately two orders in magnitude. The device had good endurance (10⁵ cycles without degradation) and long retention time (5 × 10³ s) at room temperature. The bistable switching behavior varied according to the trapping and de-trapping of charges on GO sites; the carrier transport was described using the space-charge-limited current (SCLC) model.

• Transactions on Electrical and Electronic Materials
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• 제5권4호
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• pp.148-152
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• 2004

The direct lateral profile and retention characteristics of locally trapped-charges in the nitride layer of the two-bit polysilicon-oxide-nitride-oxide-silicon (SONOS) memory are investigated by using the charge pumping method. After charges injection at the drain junction region, the lateral diffusion of trapped charges as a function of retention time is directly shown by the results of the local threshold voltage and the trapped-charges quantities.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1994년도 춘계학술대회 논문집
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• pp.127-129
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• 1994

For scale-down EEPROM, MONOS structures with the different thicknesses of gate insulators, are fabricated and the memory characteristics, such as swtching and retention characteristics are investigated. As a results, the devices with the top oxide of 20A thick were deteriorated in retentivity. However, 11V-programmable voltage for ΔV$\sub$FB/=4V and 10-year data retention were achieved in MONOS structure with the t7p oxide of 50 ${\AA}$ thick and nitride 45${\AA}$thick.

• Natural Product Sciences
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• 제22권4호
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• pp.246-251
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• 2016

This study investigated the effects of (-)-sesamin on memory deficits in 1-methyl-4-phenyl-1,2,3,6-tetrahydropyridine (MPTP)-lesioned mouse model of Parkinson's disease (PD). MPTP lesion (30 mg/kg/day, 5 days) in mice showed memory deficits including habit learning memory and spatial memory. However, treatment with (-)-sesamin (25 and 50 mg/kg) for 21 days ameliorated memory deficits in MPTP-lesioned mouse model of PD: (-)-sesamin at both doses improved decreases in the retention latency time of the passive avoidance test and the levels of dopamine, norepinephrine, 3,4-dihydroxyphenylacetic acid, and homovanillic acid, improved the decreased transfer latency time of the elevated plus-maze test, reduced the increased expression of N-methyl-D-aspartate (NMDA) receptor, and increased the reduced phosphorylation of extracellular signal-regulated kinase (ERK1/2) and cyclic AMP-response element binding protein (CREB). These results suggest that (-)-sesamin has protective effects on both habit learning memory and spatial memory deficits via the dopaminergic neurons and NMDA receptor-ERK1/2-CREB system in MPTP-lesioned mouse model of PD, respectively. Therefore, (-)-sesamin may serve as an adjuvant phytonutrient for memory deficits in PD patients.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 학술대회지
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• pp.460-462
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• 2004

The control of the data retention time is a main issue for realizing future high density dynamic random access memory. There are several leakage current mechanisms in which the stored data disappears. The mechanisms of data disappear is as follow, 1 )Junction leakage current between the junction, 2) Junction leakage current from the capacitor node contact, 3)Sub-threshold leakage current if the transfer transistor is affected by gate etch damage etc. In this paper we showed the plasma edge damage effect to find out data retention time effectiveness. First we measured the transistor characteristics of forward and reverse bias. And junction leakage characteristics are measured with/without plasma damage by HP4145. Finally, we showed the comparison TRET with etch damage, damage_cure_RTP and hydrogen_treatment. As a result, hydrogen_treatment is superior than any other method in a curing plasma etch damage side.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권1호
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• pp.1-14
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• 2001

Current status and prospects of FET-type FeRAMs (ferroelectric random access memories) are reviewed. First, it is described that the most important issue for realizing FET-type FeRAMs is to improve the data retention characteristics of ferroelectric-gate FETs. Then, necessary conditions to prolong the retention time are discussed from viewpoints of materials, device structure, and circuit configuration. Finally, recent experimental results related to the FET-type memories are introduced, which include optimization of a buffer layer that is inserted between the ferroelectric film and a Si substrate, development of a new ferroelectric film with a small remnant polarization value, proposal and fabrication of a 1T2C-type memory cell with good retention characteristics, and so on.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권1호
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• pp.40-49
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• 2001

We have developed a repeatable process of forming uniform, small-size and high-density self-assembled Si nano-crystals. The Si nano-crystals were fabricated in a conventional LPCVD (low pressure chemical vapor deposition) reactor at $620^{\circ}c$ for 15 sec. The nano-crystals were spherical shaped with about 4.5 nm in diameter and density of $5{\times}l0^{11}/$\textrm{cm}^2$. More uniform dots were fabricated on nitride film than on oxide film. To take advantage of the above-mentioned characteristics of nitride film while keeping the high interface quality between the tunneling dielectrics and the Si substrate, nitride-oxide tunneling dielectrics is proposed in n-channel device. For the first time, the single electron effect at room temperature, which shows a saturation of threshold voltage in a range of gate voltages with a periodicity of ${\Delta}Ｖ_{GS}\;{\approx}\;1.7{\;}V$, corresponding to single and multiple electron storage is reported. The feasibility of p-channel nano-crystal memory with thin oxide in direct tunneling regime is demonstrated. The programming mechanisms of p-channel nano-crystal memory were investigated by charge separation technique. For small gate programming voltage, hole tunneling component from inversion layer is dominant. However, valence band electron tunneling component from the valence band in the nano-crystal becomes dominant for large gate voltage. Finally, the comparison of retention between programmed holes and electrons shows that holes have longer retention time.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1992년도 한국자동제어학술회의논문집(국제학술편); KOEX, Seoul; 19-21 Oct. 1992
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• pp.70-73
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• 1992

This paper describes the modeling of human memory using a nerve field model which is proposed for modeling the mechanism of brain mathematically. In our model, two phases of memory, retention and recollection, are focused on. The former consists of two stages, short-term memory (STM) and long-term memory (LTM). The proposed model consists of three parts, the STM Layer, LTM Layer and the Intermediate Layer between them. Each of these is constructed by a nerve field. In the STM Layer, memorized information is retained dynamically in the form of the reverberating states of units within the layer, while in the LTM Layer, it is stored statically in the form of structures of the weight on the links between units. the Intermediate Layer is introduced to translate this dynamic representation in the STM Layer to the LTNI Layer, and also to extract the static information from the STM Layer. In addition to this, we consider the recollection of information stored in the LTM. Finally, the behavior of this model is demonstrated by computer simulation.