• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2019년도 춘계학술대회
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• pp.79-82
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• 2019

본 논문에서는 검색엔진 최적화(SEO; Search Engine Optimization)에 인공지능 기법을 접목하여, 자동화된 SEO 도구 설계 및 구현을 목표로 한다. 기존의 SEO 온-페이지(On-page) 최적화 기법들은 웹페이지 관리자들의 경험적 지식에 의존하는 한계점을 보이고 있다. 이는 SEO 성능에 영향을 끼칠 뿐 아니라, 웹페이지 관리자들에게도 SEO 도입의 장벽으로 작용한다. 따라서, 위 문제를 해결하기 위하여 메타데이터의 효과적인 구성을 위해 다음과 같은 3단계의 접근법을 제안하고자 한다. i) 상위 랭킹 웹사이트들의 메타데이터를 추출한다. ii) 어텐션 메커니즘에 기반한 LSTM(Long Short Term Memory)을 이용하여 사용자 질의어와의 관련성 높은 메타데이터를 생성한다. iii) GAN(Generative Adversarial Network) 모델을 통하여 학습함으로써 전반적으로 성능을 높여주는 기법을 제안한다. 본 연구결과는 기업의 온라인 마케팅 프로세스를 평가하고 개선하기 위한 최적화 도구로서 유용하게 활용될 것으로 기대한다.

• The Journal of the Acoustical Society of Korea
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• 제25권4E호
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• pp.137-141
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• 2006

This paper presents HE-AAC decoder optimization on TMS320C55x fixed-point DSP core using a DSP-C like FFR code, which provides fast and flexible porting to a DSP core. Our optimization efforts are focused on methodologies that include general optimization methods of FFR code suitable for general DSP or RISC platform in high-level language and software optimization methods in assembly language level. The implementation result requires 48 MIPS and 135 Kbytes memory space to decode 48 Kbps stereo using real Korean S-DMB data.

• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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• 제14권5호
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• pp.542-546
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• 2008

최근 듀얼-프로세서 기반의 모바일 내장형 시스템을 위한 듀얼-포트 SDRAM이 발표되었다. 이는 단일 메모리 칩이 두 프로세서의 로컬 메모리와 공유 메모리 역할을 모두 담당하므로 공유 메모리를 위하여 추가의 SRAM 메모리를 사용하는 기존의 구조에 비해 더 간단한 통신 구조이다. 양 포트로부터의 동시적인 접근에서의 상호배타성을 보장하기 위하여 모든 공유 메모리 접근에는 특수한 동기화 기법이 수반되어야 하는데 이는 잠재적인 성능 악화의 원인이 된다. 이 논문에서는 이러한 동기화 비용을 고려하여 듀얼-포트SDRAM 구조의 성능을 평가하고, 주 응용의 통신 특성을 고려하여 최적화한 락우선권 기법과 정적복사 기법을 제안한다. 더 나아가, 공유 뱅크를 여러 블록으로 나눔으로써 서로 다른 블록들에 대한 동시적인 접근을 가능케 하여 성능을 개선하도록 한다. 가상 프로토타이핑 환경에서 수행된 실험은 이러한 최적화 기법들이 기본 듀얼-포트SDRAM 구조에 비하여 20-50%의 성능 향상을 가져옴을 보여준다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권4호
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• pp.229-236
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• 2005

This paper presents a system level architecture evaluation technique that leverages transaction level modeling but also significantly extends it to the realm of system level performance evaluation. A major issue lies with the modeling effort. To reduce the modeling effort the proposed technique develops the concept of worst case scenarios. Since the memory controller is often found to be an important component that critically affects the system performance and thus needs optimization, the paper further addresses how to evaluate and optimize the memory controllers, focusing on the test environment and the methodology. The paper also presents an industrial case study using a real state-of-the-art design. In the case study, it is reported that the proposed technique has helped successfully find the performance bottleneck and provide appropriate feedback on time.

• Smart Structures and Systems
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• 제15권3호
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• pp.897-911
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• 2015

This study presents a novel approach based on advancements in Evolutionary Computation for data-driven modeling of complex multi-dimensional memory-dependent systems. The investigated example is a benchmark coupled three-dimensional system that incorporates 6 Bouc-Wen elements, and is subjected to external excitations at three points. The proposed technique of this research adapts Genetic Programming for discovering the optimum structure of the differential equation of an auxiliary variable associated with every specific degree-of-freedom of this system that integrates the imposed effect of vibrations at all other degrees-of-freedom. After the termination of the first phase of the optimization process, a system of differential equations is formed that represent the multi-dimensional hysteretic system. Then, the parameters of this system of differential equations are optimized in the second phase using Genetic Algorithms to yield accurate response estimates globally, because the separately obtained differential equations are coupled essentially, and their true performance can be assessed only when the entire system of coupled differential equations is solved. The resultant model after the second phase of optimization is a low-order low-complexity surrogate computational model that represents the investigated three-dimensional memory-dependent system. Hence, this research presents a promising data-driven modeling technique for obtaining optimized representative models for multi-dimensional hysteretic systems that yield reasonably accurate results, and can be generalized to many problems, in various fields, ranging from engineering to economics as well as biology.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.48-52
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• 2014

In this paper, scaling down characteristics of vertical channel phase random access memory are investigated with device simulator and finite element analysis simulator. Electrical properties of select transistor are obtained by device simulator and those of phase change material are obtained by finite element analysis simulator. From the fusion of both data, scaling properties of vertical channel phase change random access memory (VPCRAM) are considered with ITRS roadmap. Simulation of set reset current are carried out to analyze the feasibility of scaling down and compared with values in ITRS roadmap. Simulation results show that width and length ratio of the phase change material (PCM) is key parameter of scaling down in VPCRAM. Thermal simulation results provide the design guideline of VPCRAM. Optimization of phase change material in VPCRAM can be achieved by oxide sidewall process optimization.

• ETRI Journal
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• 제40권6호
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• pp.759-773
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• 2018

Uncore components such as on-chip memory systems and on-chip interconnects consume a large amount of energy in emerging embedded applications. Few studies have focused on next-generation analytical models for future chip-multiprocessors (CMPs) that simultaneously consider the impacts of the power consumption of core and uncore components. In this paper, we propose a convex-optimization approach to design heterogeneous uncore architectures for embedded CMPs. Our convex approach optimizes the number and placement of memory banks with different technologies on the memory layer. In parallel with hybrid memory architecting, optimizing the number and placement of through silicon vias as a viable solution in building three-dimensional (3D) CMPs is another important target of the proposed approach. Experimental results show that the proposed method outperforms 3D CMP designs with hybrid and traditional memory architectures in terms of both energy delay products (EDPs) and performance parameters. The proposed method improves the EDPs by an average of about 43% compared with SRAM design. In addition, it improves the throughput by about 7% compared with dynamic RAM (DRAM) design.

• 한국콘텐츠학회:학술대회논문집
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• 한국콘텐츠학회 2005년도 추계 종합학술대회 논문집
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• pp.13-18
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• 2005

실시간 렌더링(Real-Time Rendering) 기술을 사용하는 게임 및 가상현실 환경에서 3차원 데이터를 처리할 때, 텍스처는 그래픽 카드에서 지원하는 텍스처의 형식에 따라 다른 결과를 가져온다. 이 텍스처 형식에 따라 발생되는 결과를 토대로, Frame Rate, Video Memory, Quality를 비교하여 텍스처 사용에 대한 최적의 방법을 찾는 데 필요한 자료를 제시하고자 한다.

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2007년도 The 1st International Symposium on Advanced Magnetic Materials
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• pp.89.2-89.2
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• 2007

• 한국재료학회:학술대회논문집
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• 한국재료학회 2007년도 춘계학술발표대회 및 제12회 신소재 심포지엄
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• pp.14.1-14.1
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• 2007