• Title/Summary/Keyword: memory mechanism

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Electric Properties of YBCO Superconductor (YBCO 세라믹의 전기적 특성)

  • Lee, Sang-Heon
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2005.07a
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    • pp.292-293
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    • 2005
  • An electromagnetic memory effect observed in superconducting YBCO system was studied. From the measurement of differential conductance, it was cleared that the mechanism of electromagnetic memory can not be explained by using conventional flux flow model. By changing the density of external magnetic flux, changes in inductance of a coil in which a superconducting bar is inserted were also measured. It was concluded that the electromagnetic memory effect aries from the interaction between the trapped magnetic flux and the weak link of the filament formed in the superconducting bar.

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An automated memory error detection technique using source code analysis in C programs (C언어 기반 프로그램의 소스코드 분석을 이용한 메모리 접근오류 자동검출 기법)

  • Cho, Dae-Wan;Oh, Seung-Uk;Kim, Hyeon-Soo
    • The KIPS Transactions:PartD
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    • v.14D no.6
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    • pp.675-688
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    • 2007
  • Memory access errors are frequently occurred in C programs. A number of tools and research works have been trying to detect the errors automatically. However, they have one or more of the following problems: inability to detect all memory errors, changing the memory allocation mechanism, incompatibility with libraries, and excessive performance overhead. In this paper, we suggest a new method to solve these problems, and then present a result of comparison to the previous research works through the experiments. Our approach consists of two phases. First is to transform source code at compile time through inserting instrumentation into the source code. And second is to detect memory errors at run time with a bitmap that maintains information about memory allocation. Our approach has improved the error detection abilities against the binary code analysis based ones by using the source code analysis technique, and enhanced performance in terms of both space and time, too. In addition, our approach has no problem with respect to compatibility with shared libraries as well as does not need to modify memory allocation mechanism.

JMP+RAND: Mitigating Memory Sharing-Based Side-Channel Attack by Embedding Random Values in Binaries (JMP+RAND: 바이너리 난수 삽입을 통한 메모리 공유 기반 부채널 공격 방어 기법)

  • Kim, Taehun;Shin, Youngjoo
    • KIPS Transactions on Computer and Communication Systems
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    • v.9 no.5
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    • pp.101-106
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    • 2020
  • Since computer became available, much effort has been made to achieve information security. Even though memory protection defense mechanisms were studied the most among of them, the problems of existing memory protection defense mechanisms were found due to improved performance of computer and new defense mechanisms were needed due to the advent of the side-channel attacks. In this paper, we propose JMP+RAND that embedding random values of 5 to 8 bytes per page to defend against memory sharing based side-channel attacks and bridging the gap of existing memory protection defense mechanism. Unlike the defense mechanism of the existing side-channel attacks, JMP+RAND uses static binary rewriting and continuous jmp instruction and random values to defend against the side-channel attacks in advance. We numerically calculated the time it takes for a memory sharing-based side-channel attack to binary adopted JMP+RAND technique and verified that the attacks are impossible in a realistic time. Modern architectures have very low overhead for JMP+RAND because of the very fast and accurate branching of jmp instruction using branch prediction. Since random value can be embedded only in specific programs using JMP+RAND, it is expected to be highly efficient when used with memory deduplication technique, especially in a cloud computing environment.

Efficient Memory Update Module for Video Object Segmentation (동영상 물체 분할을 위한 효율적인 메모리 업데이트 모듈)

  • Jo, Junho;Cho, Nam Ik
    • Journal of Broadcast Engineering
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    • v.27 no.4
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    • pp.561-568
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    • 2022
  • Most deep learning-based video object segmentation methods perform the segmentation with past prediction information stored in external memory. In general, the more past information is stored in the memory, the better results can be obtained by accumulating evidence for various changes in the objects of interest. However, all information cannot be stored in the memory due to hardware limitations, resulting in performance degradation. In this paper, we propose a method of storing new information in the external memory without additional memory allocation. Specifically, after calculating the attention score between the existing memory and the information to be newly stored, new information is added to the corresponding memory according to each score. In this way, the method works robustly because the attention mechanism reflects the object changes well without using additional memory. In addition, the update rate is adaptively determined according to the accumulated number of matches in the memory so that the frequently updated samples store more information to maintain reliable information.

Anticipatory I/O Management for Clustered Flash Translation Layer in NAND Flash Memory

  • Park, Kwang-Hee;Yang, Jun-Sik;Chang, Joon-Hyuk;Kim, Deok-Hwan
    • ETRI Journal
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    • v.30 no.6
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    • pp.790-798
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    • 2008
  • Recently, NAND flash memory has emerged as a next generation storage device because it has several advantages, such as low power consumption, shock resistance, and so on. However, it is necessary to use a flash translation layer (FTL) to intermediate between NAND flash memory and conventional file systems because of the unique hardware characteristics of flash memory. This paper proposes a new clustered FTL (CFTL) that uses clustered hash tables and a two-level software cache technique. The CFTL can anticipate consecutive addresses from the host because the clustered hash table uses the locality of reference in a large address space. It also adaptively switches logical addresses to physical addresses in the flash memory by using block mapping, page mapping, and a two-level software cache technique. Furthermore, anticipatory I/O management using continuity counters and a prefetch scheme enables fast address translation. Experimental results show that the proposed address translation mechanism for CFTL provides better performance in address translation and memory space usage than the well-known NAND FTL (NFTL) and adaptive FTL (AFTL).

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Organizational Memory Formulation by Inference Diagram

  • Lee, Kun-Chang;Nho, Jae-Bum
    • Proceedings of the Korean Operations and Management Science Society Conference
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    • 1999.10a
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    • pp.42-46
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    • 1999
  • Knowledge management(KM) is emerging as a robust management mechanism with which an organization can remain highly intelligent and competitive in a turbulent market. Organization memory(or knowledge) is at the heart of KM success. How to create organizational memory has been debated among researchers. In literature, a wide variety of methods for creating organizational memory have been proposed only to prove that its applicability is limited to decision-making problems which require shallow or non-causal knowledge type. However, organizational memory with a sense of causal knowledge is highly required in solving complicated decision-making problems in which complex dynamics exist between various factors and influence each other with cause and effect relationship among them. In this respect, we propose a new approach to creating a causal-typed organizational memory (CATOM), which has a form of causal knowledge and is represented in a matrix form, by using an inference diagram. An algorithm for CATOM creation is suggested and applied to an illustrative example. Results show that our proposed KM approach can effectively equip an organization with semi-automated CATOM creation and inference process which is deemed useful in a highly competitive business environment.

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A Study on the Shape Memory Characteristic Behaviors of Ti-42.5at.%Ni-2.0at.%Cu Alloys in Tension and Compression Condition (Ti-42.5at.%Ni-2.0at.%Cu합금의 인장 및 압축에 따른 형상기억특성에 관한 연구)

  • Woo, Heung-Sik;Cho, Jae-Whan;Park, Yong-Gyu
    • Journal of the Korean Society of Safety
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    • v.24 no.5
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    • pp.1-5
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    • 2009
  • NiTiCu alloys can produce a large force per unit volume and operate with a simple mechanism. For this reasons, it has been widely studied for application as a micro actuator. So in this study, one-way and two way shape memory effects of Ti-42.5at%Ni-2.0at%Cu alloys are studied. In the case of one-way shape memory effects, shape memory recoverable stress and strain of this alloys were measured by means of tension and compression tests under constant temperature. The strains by tension and compression stress were perfectly recovered by heating at any testing conditions also shape memory recoverable stress increased to 116 MPa in tension tests and to 260 MPa in compression tests. In the case of two-way shape memory effects, transformation temperatures from thermal cycling under constant uniaxial applied tension and compression loads linearly increased by increasing external loads and their maximum recoverable strain is 3.8% at 100MPa tensile condition and 2.2% at 125 MPa compression condition.

Performance of the Maximum-Likelihood Detector by Estimation of the Trellis Targets on the Sixteen-Level Cell NAND Flash Memory (16레벨셀 낸드 플래시 메모리에서 트렐리스 정답 추정 기법을 이용한 최대 유사도 검출기의 성능)

  • Park, Dong-Hyuk;Lee, Jae-Jin
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.47 no.7
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    • pp.1-7
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    • 2010
  • In this paper, we use the maximum-likelihood detection by the estimation of trellis targets on the 16-level cell NAND flash memory. This mechanism has a performance gain by using a maximum-likelihood detector. The NAND flash memory channel is a memory channel because of the coupling effect. Thus, we use the known data arrays to finding the targets of trellis. The maximum-likelihood detection by proposed scheme performs better than the threshold detection on the 16-level cell NAND flash memory channel.

Size Reduction and Performance Analysis of the Bit-map Table Used in the Bus-based Shared Memory System (버스기반의 공유메모리 시스템에서 사용된 비트맵 테이블의 크기 축소와 성능 분석)

  • Woo, Jong-Jung;Lee, Ka-Young
    • The Transactions of the Korea Information Processing Society
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    • v.5 no.1
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    • pp.24-32
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    • 1998
  • The bus contention among bus-based shared-memory multiprocessors limits their performance. In addition, under split bus transaction environment, multiprocessors may make some memory requests unnecessary stand by in the memory access buffer, which makes system performance worse. This unnecessary stand-by can be eliminated by maintaining the bitmap table which contains the status bit for each memory block. However, this mechanism requires a great size of SRAM for the status information, which is fully mapped from the whole memory blocks. To solve this problem, we propose a bitmap cache which exploits partial mapping and locality of references. The simulation results show that the proposed system can greatly reduce the capacity of SRAM for the status information with little deteriorating its performance.

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Switching characteristics of the Scaled MONOS Nonvolatile Memory Devices (Scaled MONOS 비휘발성 기억소자의 스위칭 특성)

  • 이상배;김선주;이성배;강창수;서광열
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1995.05a
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    • pp.54-57
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    • 1995
  • This study is to investigate the switching charac-teritics in the5V-programmable scaled MONOS nonvolatile memory devices, Modified Folwer-Nordheim tunneling mechanism become important when the electric field in the tunneling oxide is 6 MV/cm for E$\_$OT/ <6MV/cm the trap-assisted tunneling mechanism is dominant, The density of nitride bulk trap is found to be N$\_$T/=7.7${\times}$10$\^$18/ cm$\^$-3/ and the energy level of trap is determined to be ø$\_$T/=0.65 eV.

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