• 한국전기전자재료학회논문지
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• 제19권10호
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• pp.918-922
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• 2006

Chalcogenide Phase change memory has the high performance necessary for next-generation memory, because it is a nonvolatile memory with high programming speed, low programming voltage, high sensing margin, low power consumption and long cycle duration. To minimize the power consumption and the program voltage, the new composition material which shows the better phase-change properties than conventional $Ge_2Sb_2Te_5$ device has to be needed by accurate material engineering. In the present work, we investigate the basic thermal and the electrical properties due to phase-change compared with chalcogenide-based new composition $Ge_1Se_1Te_2$ material thin film and convetional $Ge_2Sb_2Te_5$ PRAM thin film. The fabricated new composition $Ge_1Se_1Te_2$ thin film exhibited a successful switching between an amorphous and a crystalline phase by applying a 950 ns -6.2 V set pulse and a 90 ns -8.2 V reset pulse. It is expected that the new composition $Ge_1Se_1Te_2$ material thin film device will be possible to applicable to overcome the Set/Reset problem for the nonvolatile memory device element of PRAM instead of conventional $Ge_2Sb_2Te_5$ device.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.95-96
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• 2009

A fully depleted capacitorless 1-transistor dynamic random access memory (FD 1T-DRAM) based on a sSOI strained-silicon-on-insulator) wafer was investigated. The fabricated device showed excellent electrical characteristics of transistor such as low leakage current, low subthreshold swing, large on/off current ratio, and high electron mobility. The FD sSOI 1T-DRAM can be operated as memory device by the floating body effect when the substrate bias of -15 V is applied, and the FD sSOI 1T-DRAM showed large sensing margin and several milli seconds data retention time.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.346-346
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• 2010

A capacitorless one transistor dynamic random access memory (1T-DRAM) on silicon-germanium-on-insulator substrate was investigated. SGOI technology can make high effective mobility because of lattice mismatch between the Si channel and the SiGe buffer layer. To evaluate memory characteristics of 1T-DRAM, the floating body effect is generated by impact ionization (II) and gate induced drain leakage (GIDL) current. Compared with use of impact ionization current, the use of GIDL current leads to low power consumption and larger sense margin.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권2호
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• pp.87-89
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• 2006

This paper proposes a sense amplifier with non-volatile memory in order to improve the image quality of LCD by enhancing the matching of the driving voltages between the panel and driver. The sense amplifier having a wide sensing margin and fast response adjusts LCD driver voltage of display driver. The CSTN-LCD with the sense amplifier results improved image quality than that with conventional 6 bit column driver without it.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권2호
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• pp.110-116
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• 2004

We propose a novel sensing scheme, which operates by sensing the difference in voltage between a memory cell and a reference cell for a magneto-resistive random access memory (MRAM). A new midpoint-reference generation circuit is adopted for the reference cell to improve the sensing margin and to guarantee correct operation of sensing circuit for wide range of tunnel magneto resistance (TMR) voltages. In this scheme, the output voltage of the reference cell becomes nearly the midpoint between the cell voltages of high and low states even if the voltage across the magnetic tunnel junction (MTJ) varies.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권3호
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• pp.374-380
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• 2015

As semiconductor devices are being scaled down, random variation becomes a critical issue, especially in the case of static random access memory (SRAM). Thus, there is an urgent need for statistical methodologies to analyze the impact of random variations on the SRAM. In this paper, we propose a novel sampling method based on the concept of a confidence ellipse. Results show that the proposed method estimates the SRAM margin metrics in high-sigma regimes more efficiently than the standard Monte Carlo (MC) method.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2009년도 춘계학술발표대회
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• pp.19.1-19.1
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• 2009

Phase change random access memory (PRAM)은 large sensing signal margin, fast programming speed, low operation voltage, high speed operation, good data retention, high scalability등을 가지는 가장 유망한 차세대 비휘발성 메모리이다. 현재 PRAM용 상변화 재료로는 주로 Ge2Sb2Te5가 사용되고 있지만 reset 전류가 높고 reliability 가 좋지 않아서 새로운 상변화 물질 연구가 필요하다. AgInSbTe (AIST)는 GST와 더불어 열에 의한 가역적 상변화를 하는 소재로 광기록 매체에서는 기록 속도가 빠르고 동작 특성이 우수하다는 특징이 있다. 본 연구에서는 XRD, 비저항측정등을 통해 온도에 따른 AIST의 물성 및 결정화 특성을 분석하고 나노 소자제작을 통해 그 전기적 특성을 평가하였다.

• International journal of advanced smart convergence
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• 제11권2호
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• pp.1-6
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• 2022

With the emergence of the new era of the 4th industrial revolution, compute-bound workloads with large memory footprint like big data processing increase dramatically. Even in such compute-bound workloads, however, we observe bulky I/Os while loading big data from storage to memory. Although file I/O cache plays a role of accelerating the performance of storage I/O, we found out that the cache hit rate in such environments is not improved even though we increase the file I/O cache capacity because of some special I/O references generated by compute-bound workloads. To cope with this situation, we propose a new file I/O cache management policy that improves the cache hit rate for compute-bound workloads significantly. Trace-driven simulations by replaying file I/O reference logs of compute-bound workloads show that the proposed cache management policy improves the cache hit rate compared to the well-acknowledged CLOCK algorithm by a large margin.

• Journal of information and communication convergence engineering
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• 제22권2호
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• pp.98-108
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• 2024

Scrypt is a password-based key derivation function proposed by Colin Percival in 2009 that has a memory-hard structure. Scrypt has been intentionally designed with a memory-intensive structure to make password cracking using ASICs, GPUs, and similar hardware more difficult. However, in this study, we thoroughly analyzed the operation of Scrypt and proposed strategies to maximize computational parallelism in GPU environments. Through these optimizations, we achieved an outstanding performance improvement of 8284.4% compared with traditional CPU-based Scrypt computations. Moreover, the GPU-optimized implementation presented in this paper outperforms the simple GPU-based Scrypt processing by a significant margin, providing a performance improvement of 204.84% in the RTX3090. These results demonstrate the effectiveness of our proposed approach in harnessing the computational power of GPUs and achieving remarkable performance gains in Scrypt calculations. Our proposed implementation is the first GPU implementation of Scrypt, demonstrating the ability to efficiently crack Scrypt.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2011년도 춘계학술대회
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• pp.129-131
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• 2011

Hight speed memory application을 위하여 6.4-Gb/s/channel 4-PAM transceiver가 제안된다. Voltage margin과 time margin용 증가시키기 위하여 asymmetric 4-PAM scheme과 이를 위한 회로를 제안한다. 제안된 asymmetric 4-PAM scheme은 기존 회로에 비하여 송신단에서 33%의 기준전압 노이즈 영향을 줄인다. Channel의 ISI를 줄이기 위해서 transmitter의 1-tap pre-emphasis가 사용된다. 제안된 asymmetric 4-PAM transceiver는 1.2V supply 0.13um 1-poly 6-metal CMOS 공정에서 구현되었다. PLL을 포함한 1-channel transceiver의 면적과 전력소모는 각각 $0.294um^2$와 6mW이다.