• The Journal of the Korea Contents Association
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• v.14 no.3
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• pp.22-32
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• 2014

Recently, GPGPU has been widely used for general-purpose processing as well as graphics processing by providing optimized hardware for parallel processing. Memory system has big effects on the performance of parallel processing units such as GPU. In the GPU, hierarchical memory architecture is implemented for high memory bandwidth. Moreover, both memory address coalescing and memory request merging techniques are widely used. This paper analyzes the GPU performance according to various memory organizations. According to our simulation results, GPU performance improves by 15.5%, 21.5%, 25.5%, 30.9% as adding 8KB L1, 16KB L1, 32KB L1, 64KB L1 cache, respectively, compared to case without L1 cache. However, experimental results show that some benchmarks decrease performance since memory transaction increases due to data dependency. Moreover, average memory access latency is increased as the depth of hierarchical cache level increases when cache miss occurs significantly.

• Korean Journal of Cognitive Science
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• v.11 no.3_4
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• pp.83-93
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• 2000

The effect of immediate and delayed recognition memory on event-related potential (ERP) was studied using a continuous recognition memory task and event-related potential (ERP). Among 240 stimulus words 40 words were not repeated. 100 were immediately repeated and 100 were repeated after 5 intervening words. All words presented only once during the experiment were referred to as new words. Subjects responded faster and more accurately to words repeated immediately than to new words a and to those repeated after intervening words. In terms of ERP results the immediately repeated words were associated with large P300 amplitude, early P300 latency and a absence of N400. while words repeated after a delay were associated with small P300 a amplitude. late P300 latency and the presence of N400. N400 was elicited only to new w words and to those repeated after a delay. The general morphology of the waveform was s similar for three stimulus-presentation conditions until around 3l0ms after the onset of stimulus. These results indicate that immediate and delayed recognition memory could be dissociated into two distinct processes possibly being mediated by different cerebral mechanism, and the dissociation between two types of recognition memory emerges around 3l0ms poststim'ulus. The immediate and delayed recognition memory for words are considered in terms of template matching and memory searching.

• Journal of the Korea Society of Computer and Information
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• v.22 no.4
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• pp.25-32
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• 2017

Recently, the use of NAND flash memory is being increased as a secondary device to displace conventional magnetic disk. NAND flash memory, as one among non-volatile memories, has many advantages such as low power, high reliability, low access latency, and so on. However, NAND flash memory has disadvantages such as erase-before-write, unbalanced operation speed, and limited P/E cycles, unlike conventional magnetic disk. To solve these problems, NAND flash memory mainly adopted FTL (Flash Translation Layer). In particular, garbage collection technique in FTL tried to improve the system lifetime. However, previous garbage collection techniques have a sensitive property of the system lifetime according to write pattern. To solve this problem, we propose BSGC (Balanced Selection-based Garbage Collection) technique. BSGC efficiently selects a victim block using all intervals from the past information to the current information. In this work, SFL (Search First linked List), as the proposed block allocation policy, prolongs the system lifetime additionally. In our experiments, SFL and BSGC prolonged the system lifetime about 12.85% on average and reduced page migrations about 22.12% on average. Moreover, SFL and BSGC reduced the average response time of 16.88% on average.

• Journal of Physiology & Pathology in Korean Medicine
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• v.31 no.5
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• pp.270-276
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• 2017

The aim of this study was to investigate the effects of the water extract of Albizziae Cortex (AC) on the learning and memory impairments. AC was administered to normal mouse and scopolamine-injected amnesia mouse model. Passive avoidance test, Y-maze test, and Morris water maze test were conducted to confirm the cognitive-enhancing activities of AC. Acetylcholinesterase (AChE) activity and acetylcholine (Ach) content were measured after oral administration of AC. On the passive avoidance test, AC (200 mg/kg) significantly increased latency time and recovered scopolamine-impaired learning and memory in mice. In addition, AC (200 mg/kg) reduced Exploration time in target quadrant and reversed the scopolamine-induced cognitive impairments in the Y-maze test. Moreover, AC (200 mg/kg) increased exploration time in target quadrant and improved scopolamine-reduced escape latencies in the Morris water maze test. These effects were presented by regulatory effects of AC on AChE activity and Ach content. Taken together, AC increases cognitive-enhancing activities and ameliorates scopolamine-induced learning and memory impairment. AC might be a potential agent for prevention and treatment of amnesia and dementia.

• Journal of the Korean Society of Food Culture
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• v.36 no.6
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• pp.633-639
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• 2021

Raphanus sativus var. hortensis f. raphanistroides Makino (Korean wild radish [WR]) are root vegetables belonging to the Brassicaceae family. These radish species mostly grow in sea areas in Asia, where they have been traditionally used as a medicinal food to treat various diseases. To investigate the effect of WR on neuronal cell death in SH-SY5Y cells, beta-amyloid was used to develop the cell death model. WR attenuated neuronal cell death in SH-SY5Y and regulated the mitogen-activated protein kinase (MAPK) signaling. WR extract also inhibited acetylcholinesterase inhibitor activity. Additionally, the WR treatment group ameliorated the behavior of the memory-impaired mice in a scopolamine-induced mouse model. In the behavior test, WR treated mice showed shorter escape latency and swimming distance and improved the platform-crossing number and the swimming time within the target quadrant. Furthermore, WR prevented histological loss of neurons in hippocampal CA1 regions induced by scopolamine. This study shows that WR can prevent memory impairment which may be a crucial way for the prevention and treatment of memory dysfunction and neuronal cell death.

• Biomolecules & Therapeutics
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• v.17 no.3
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• pp.249-255
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• 2009

Forsythiaside is a polyphenolic constituent of the fruits of Forsythia suspense Vahl which are widely used as anti-inflammatory herbal raw materials in traditional Chinese medicine. In the present study, the authors assessed the effects of forsythiaside on learning and memory impairments induced by scopolamine using a passive avoidance and the Morris water maze tests in mice. Drug-induced amnesia was induced by scopolamine treatment (1 mg/kg, i.p.). Forsythiaside (10 mg/kg, p.o) administration significantly prevented scopolamine-induced step-through latency reduction in the passive avoidance test and scopolamine-induced increased escape latency in the Morris water maze test (p<0.05). Moreover, in an ex-vivo study, forsythiaside treatment (10 mg/kg, p.o) significantly reduced the increase of thiobarbituric acid reactive substance levels induced by scopolamine (p<0.05). Taken together, the present study suggests that forsythiaside could be useful for the treatment of cognitive impairment, and that its beneficial effects are mediated, in part, by its antioxidative properties.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.6
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• pp.594-598
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• 2008

In this paper we propose a fast booting technique based on Improved snapshot boot in embedded Linux, widely adopted in personal devices such as PDA and mobile phones. The existing Snapshot boot technique tries to create a snapshot image at the time of suspend, and later load the entire snapshot image into the system memory at the predefined location with the help of a bootloader at the time of resume. Since a bootloader has to copy the entire snapshot image into the predefined memory to resume the previous suspended computing state, a little bit long time is required to resume. Improved snapshot boot does not create a snapshot image consisting of whole memory pages at the time of suspend, thus resulting in smaller snapshot image than the existing snapshot boot. The remaining pages are in the swap area. The resulting smaller sized snapshot image enables much faster booting latency. Through the experiment, we can see the booting latency is reduced almost 30% with suspend image of 2982 pages. This result depends on the amount of swap-out pages.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.8
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• pp.473-486
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• 2004

NUMA systems have remote access caches(RAC) in each local node to reduce the overhead for repeated remote memory accesses. By this RAC, memory latency and network traffic can be reduced and the performance of the multiprocessor system can be improved. Until now, several cache replacement policies have been proposed in recent years, and there also is cache replacement policy for multiprocessor systems. In this paper, we propose a cache replacement policy which is based on cache line coherence information. In this policy, the cache line that does not have an ownership is replaced first with respect to cache line that has an ownership. Like this way, the overhead to transfer ownership is avoided and the memory latency can be decreased. We also propose “Keeping-Ownership replacement policy with MRU (KOM)” and “Keeping-Ownership replacement policy with Reference Bit(KORB)” to reduce the frequent replacement penalty of the ownership-lacking cache line. We compare and analyze these with LRU and Pseudo LRU(PLRU). The simulation shows that KOM outperforms the PLRU by 25%, and KORB outperforms the PLRU by 13%. Although the hardware cost of KOM is very small, the performance of KOM is nearly equal to that of the LRU.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.9
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• pp.1382-1391
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• 2022

White-box cryptography can respond to white-box attacks that can access and modify memory by safely hiding keys in the lookup table. However, because the size of lookup tables is large and the speed of encryption is slow, it is difficult to apply them to devices that require real-time while having limited resources, such as IoT(Internet of Things) devices. In this work, we propose a scheme for collecting short-length plaintexts and processing them at once, utilizing the characteristics that white-box ciphers process encryption on a lookup table size basis. As a result of comparing the proposed method, assuming that the table sizes of the Chow and XiaoLai schemes were 720KB(Kilobytes) and 18,000KB, respectively, memory usage reduced by about 29.9% and 1.24% on average in the Chow and XiaoLai schemes. The latency was decreased by about 3.36% and about 2.6% on average in the Chow and XiaoLai schemes, respectively, at a Traffic Load Rate of 15 Mbps(Mega bit per second) or higher.

• Journal of KIISE
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• v.42 no.4
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• pp.427-433
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• 2015

The rapid advancement of computing technology has triggered the need for fast data I/O processing and high-performance storage technology. Next generation memory technology, which we refer to as new memory, is anticipated to be used for high-performance storage as they have excellent characteristics as a storage device with non-volatility and latency close to DRAM. This research proposes NTL (New memory Translation layer) as a technology to make use of new memory as storage. With the addition of NTL, conventional I/O is served with existing mature disk-based file systems providing compatibility, while new memory I/O is serviced through the NTL to take advantage of the byte-addressability feature of new memory. In this paper, we describe the design of NTL and provide experiment measurement results that show that our design will bring performance benefits.