• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.743-744
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• 2006

This paper presents implementation of parallel processing system for image processing. The parallel processing system proposed consisted of 16 processing elements, and multi-access memory system, and interface modules. The multi-access memory system we introduced is made up of a memory module selection, a data routing module, and an address calculation and routing module.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2002년도 추계종합학술대회
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• pp.800-803
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• 2002

The MONOS capacitor are fabricated to investigate the carrier trapping due to Fowler-Nordheim tunneling injection. The carrier trapping in scaled multi-dielectric(ONO) depends on the nitride and Op oxide thickness under Fowler_Nordheim tunneling injection. Carriers captured at nitride film could not escape from nitride to gate, but be captured at top oxide and nitride interface traps because of barrier height of top oxide. Therefore, it is expected that the MONOS memory devices using multi dielectric films enhance memory effect and have a long memory retention characteristic.

• 한국시뮬레이션학회:학술대회논문집
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• 한국시뮬레이션학회 2001년도 춘계 학술대회 논문집
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• pp.153-156
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• 2001

We have developed CNS(Compact Nuclear Simulator) which can be used for the fundamental training of the nuclear power plant operators. The application software for CNS consists of simulation engine(analyzer code), instructor station software, and man-machine interface software. Each application software is regarded as one black box and the communication of black boxes is performed by the predefined shared memory variables. In this paper, we discuss our experience for CNS development.

• 대한전자공학회논문지
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• 제27권6호
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• pp.901-909
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• 1990

With a wide spread of 32 bit personal computers, a simple structure and high performance memory system have been highly required. In this paper, a memory block is constructed by using a modified hierarchical bit line in which the DRAM bit line and the latch which works as a SRAM cell are integrated by an interface gate. And the new architecture memory DSRAM(Dynamic Static RAM) is proposed by interleaving the 16 memory block. Because the DSRAM works with 16 page, the page is miss ratio becomes small and the RAS precharge time which is incurred by page miss is shortened. So the DSRAM can implement an optimum page interleaving and it has good compatibility to the existing DRAMs. The DSRAM can be widely used in small computers as well as a high performance memory system.

• 전자통신동향분석
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• 제37권1호
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• pp.42-52
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• 2022

With the advent of the big data era, the memory capacity required for computing systems is rapidly increasing, especially in High Performance Computing systems. However, the number of DRAMs that can be used in a computing node is limited by the structural limitations of the hardware (for example, CPU specifications). Memory expansion technology has attracted attention as a means of overcoming this limitation. This technology expands the memory capacity by leveraging the external memory connected to the host system through hardware interface such as PCIe and CCIX. In this paper, we present an overview and describe the development trends of the memory expansion technology. We also provide detailed descriptions and use cases of the CCIX that provides higher bandwidth and lower latency than cases of the PCIe.

• International journal of advanced smart convergence
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• 제12권1호
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• pp.76-81
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• 2023

Journaling file systems are widely used to keep file systems in a consistent state against crash situations. As traditional journaling file systems are designed for block I/O devices like hard disks, they are not efficient for emerging byte-addressable NVM (non-volatile memory) media. In this article, we present a new in-memory journaling file system for NVM that is different from traditional journaling file systems in two respects. First, our file system journals only modified portions of metadata instead of whole blocks based on the byte-addressable I/O feature of NVM. Second, our file system bypasses the heavy software I/O stack while journaling by making use of an in-memory file system interface. Measurement studies using the IOzone benchmark show that the proposed file system performs 64.7% better than Ext4 on average.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.34-39
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• 2014

This paper discusses the 3-level charge pumping (CP) method in planar-type Silicon-Oxide-High-k-Oxide-Silicon (SOHOS) and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) devices to find out the reason of the degradation of data retention properties. In the CP technique, pulses are applied to the gate of the MOSFET which alternately fill the traps with electrons and holes, thereby causing a recombination current Icp to flow in the substrate. The 3-level charge pumping method may be used to determine not only interface trap densities but also capture cross sections as a function of trap energy. By applying this method, SOHOS device found to have a higher interface trap density than SONOS device. Therefore, degradation of data retention characteristics is attributed to the many interface trap sites.

• E2M - 전기 전자와 첨단 소재
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• 제7권3호
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• pp.231-235
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• 1994

The multi-dielectric layer $SiO_2$/$Si_3{N_4}$/$SiO_2$ (ONO) is used to improve charge retention and to scale down the memory device. The nitride layer of MNOS device is oxidize to form ONO system. During the oxidation of the nitride layer, the change of thickness of nitride layer and generation of interface state between nitride layer and top oxide layer occur. In this paper, effects of oxidation of the nitride layer is studied. The decreases of the nitride layer due to oxidation and trapping characteristics of interface state of multi layer dielectric film are investigated through the C-V measurement and F-N tunneling injection experiment using SONOS capacitor structure. Based on the experimental results, carrier trapping model for maximum flatband voltage shift of multi layer dielectric film is proposed and compared with experimental data. As a results of curve fitting, interface trap density between the top oxide and layer is determined as being $5{\times}10^11$~$2{\times}10^12$[$eV^1$$cm^2$].

• 마이크로전자및패키징학회지
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• 제19권1호
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• pp.67-73
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• 2012

본 연구는 고밀도 미세회로 형성 및 원가절감에 유리한 페이스트의 인쇄/건조, 프리프레그 관통 및 적층 공법을 이용한 $B^2it$ 공법을 이용하여 FMC 기판을 제조한 후 열적 스트레스에 대한 범프의 계면반응 연구를 수행하였다. 열적 스트레스에 대한 Ag 범프의 접합 신뢰성을 조사하기 위해 열충격시험, 열응력시험을 수행한 후 전기적 특성 및 단면분석을 통해 균열발생 여부를 조사하였다. 또한 Ag 범프와 Cu 랜드의 접합계면에 대한 계면반응 특성을 분석하기 위해 주사전자현미경(SEM), 에너지분산스펙트럼(EDS) 및 FIB분석을 수행하여 계면에서 발생되는 확산반응을 분석하였다. 이러한 결과를 바탕으로 열적 스트레스에 대한 Ag 페이스트 범프/Cu 랜드 접합계면에서 계면반응에 의해 형성된 Ag-Cu 합금층을 확인할 수 있었다. 이러한 합금층은 Cu ${\rightarrow}$ Ag 보다, Ag ${\rightarrow}$ Cu 로의 확산속도가 빠르기 때문에, Cu층에서의 (Ag, Cu) 합금층이 보다 많이 관찰되었으며, 합금층이 Ag범프의 계면 접합력 향상에 기여하는 것을 알 수 있었다.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2002년도 봄 학술발표논문집 Vol.29 No.1 (A)
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• pp.616-618
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• 2002

최근에는 고성능 네트웍으로 구성된 클러스터 상에서 사용자 수준 통신을 사용하는 소프트웨어 분산 공유메모리 시스템의 연구가 활발히 진행되고 있다. 본 논문에서는 사용자수준 프로토콜의 표준인 Virtual Interface Architecture(VIA)를 사용하고 확장성 있는 Home-based Lazy release Consistency(HLRC) 모델을 기반으로 하는 소프트웨어 분산공유메모리 시스템을 구현한다. 본 시스템은 VIA의 원격 메모리 쓰기 기능을 최대한 활용하며, 통신 과정에서 통신 버퍼와 사용자 메모리 사이의 복사가 일어나지 않도록 설계되어 높은 성능을 보인다.