• Title/Summary/Keyword: memory interface

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A Design of Programmable Fragment Shader with Reduction of Memory Transfer Time (메모리 전송 효율을 개선한 programmable Fragment 쉐이더 설계)

  • Park, Tae-Ryoung
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.12
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    • pp.2675-2680
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    • 2010
  • Computation steps for 3D graphic processing consist of two stages - fixed operation stage and programming required stage. Using this characteristic of 3D pipeline, a hybrid structure between graphics hardware designed by fixed structure and programmable hardware based on instructions, can handle graphic processing more efficiently. In this paper, fragment Shader is designed under this hybrid structure. It also supports OpenGL ES 2.0. Interior interface is optimized to reduce the delay of entire pipeline, which may be occurred by data I/O between the fixed hardware and the Shader. Interior register group of the Shader is designed by an interleaved structure to improve the register space and processing speed.

Design and Implementation of the Java Card API for Efficient File Management (효율적 파일 관리를 위한 자바카드 API 설계 및 구현)

  • Song Young-Sang;Shin In-Chul
    • The KIPS Transactions:PartC
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    • v.13C no.3 s.106
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    • pp.275-282
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    • 2006
  • There are several independent applets to support various applications in a Java Card. Each applet in a Java Card processes and manages its own data without concern to other applets and their data. In this paper we proposed file system API to support efficient file management based on Java Card. Also we designed and implemented Java Card based file system API using basic API and referring to the file system standard defined in ISO 7816-4 Smart Card standard. By using proposed file system API, we can replace duplications of same code in each applet with short method call. So the used memory space and processing time is reduced and also the reduction of development time and cost will be expected.

Research on the Waveform Generator Technology for the SAR Payload

  • Won, Young-Jin;Youn, Young-Su;Kim, Jin-Hee
    • The Bulletin of The Korean Astronomical Society
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    • v.37 no.2
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    • pp.228.1-228.1
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    • 2012
  • Digital waveform generation technology for SAR payload can be divided into DDS(Direct Digital Synthesizer) method and Memory Mapped(M/M) method. DDS is the single chip which consists of the Sine Table, NCO(Numerically Controlled Oscillator), DAC, and so on. DDS method is a very simple method because the circuit configuration is not complex but has a disadvantage that can not control phase and amplitude easily by using NCO. M/M method has the complexity of the circuit configuration because it requires the memories which stores the waveforms, the control circuits, and DAC. And this method should apply the high interface technology for being compatible with the wide bandwidth of the digital signal and has the difficulty for PCB design because the number of the signal lines should be increased according to the number of the data bits for DAC. Although it has several disadvantages, this method has the capability of pre-distortion function which can compensate the phase and amplitude characteristics of the system and also has an excellent advantage to make any arbitrary waveform, so this method is considered as an important technology with DDS method. This research describes the technological trends of the waveform generator for the SAR payload and analyzes the characteristics of the technology.

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Sketch-based Solid Prototype Modeling System with Dual Data Structure of Point-set Surfaces and Voxels

  • Takeuchi, Ryota;Watanabe, Taichi;Yamakawa, Soji
    • International Journal of CAD/CAM
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    • v.11 no.1
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    • pp.18-26
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    • 2011
  • This paper proposes a new solid-shape modeling system based on a lusterware-image illustration. The proposed method reconstructs a three dimensional solid shape from a set of rough sketches that are typically drawn in the early stages of the design process. The sketches do not have to be strictly accurate, and this tolerance to the roughness of the input sketches is one of the major advantages of the proposed method. The proposed system creates an initial shape based on the silhouette of the input lusterware-images. Then the user can edit the initial shape with intuitive cutting and dishing-up operations, which are based on sketching user interface. To achieve the goal, the system retains the geometric model with two representations: a point-set data and a volume data. This dual data structure allows the program to create an initial shape from the input images with little computational cost, and the user can apply cutting and dishing-up operations without substantially increasing computational and memory requirements. In this research, we have tested the proposed system by reconstructing solid models of some mechanical parts from rough sketches. The experimental results indicate that the proposed method is useful for the prototyping of a solid shape.

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A Real-Time Monitoring System Model for Reducing Manufacturing Lead-Time in Numerical Control Process - Focusing on the Marine Engine Block Process - (제조 리드타임 단축을 위한 NC 가공공정에서의 실시간 모니터링 시스템 모형 - 선박용 엔진블록 가공공정을 중심으로 -)

  • Kong, Myung-Dal
    • Journal of the Korea Safety Management & Science
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    • v.20 no.3
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    • pp.11-19
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    • 2018
  • This study suggests a model of production information system that can reduce manufacturing lead time and uniformize quality by using DNC S/W as a part of constructing production information management system in the industrial field of the existing marine engine block manufacturing companies. Under the effect of development of this system, the NC machine interface device can be installed in the control computer to obtain the quality information of the workpiece in real time so that the time to inspect the process quality and verify the product defect information can be reduced by more than 70%. In addition, the reliability of quality information has been improved and the external credibility has been improved. It took 30 minutes for operator to obtain, analyze and manage the quality information when the existing USB memory is used, but the communication between the NC controller computer and the NC controller in real time was completed to analyze the workpiece within 10 seconds.

Design of a Rule-Based Solution Based on MFC for Inspection of the Hybrid Electronic Circuit Board (MFC 기반 하이브리드 전자보오드 검사를 위한 규칙기반 솔루션 설계)

  • Ko Yun-Seok
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.54 no.9
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    • pp.531-538
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    • 2005
  • This paper proposes an expert system which is able to enhance the accuracy and productivity by determining the test strategy based on heuristic rules for test of the hybrid electronic circuit board producted massively in production line. The test heuristic rules are obtained from test system designer, test experts and experimental results. The guarding method separating the tested device with circumference circuit of the device is adopted to enhance the accuracy of measurements in the test of analog devices. This guarding method can reduce the error occurring due to the voltage drop in both the signal input line and the measuring line by utilizing heuristic rules considering the device impedance and the parallel impedance. Also, PSA(Parallel Signature Analysis) technique Is applied for test of the digital devices and circuits. In the PSA technique, the real-time test of the high integrated device is possible by minimizing the test time forcing n bit output stream from the tested device to LFSR continuously. It is implemented in Visual C++ computer language for the purpose of the implementation of the inference engine using the dynamic memory allocation technique, the interface with the electronic circuit database and the hardware direct control. Finally, the effectiveness of the builded expert system is proved by simulating the several faults occurring in the mounting process the electronic devices to the surface of PCB for a typical hybrid electronic board and by identifying the results.

A Real-Time Expert System for the High Reliability of Railway Electronic Interlocking System (철도 전자연동장치의 고신뢰화를 위한 실시간 전문가 시스템)

  • Go, Yun-Seok;Choe, In-Seon;Gwon, Yong-Hun
    • The Transactions of the Korean Institute of Electrical Engineers A
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    • v.48 no.11
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    • pp.1457-1463
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    • 1999
  • This paper develops an real-time expert system for the electronic interlocking system. it obtains the higher safety by determining the railway interlocking strategy in order to prevent trains from colliding, and derailing in the viewpoint of veteran expert, considering the situation of station in real-time. The expert system determines the real-time interlocking strategy by confirming the interlocking relationships among signal facilities based on the interlocking knowledge base from input information such as signal, points, and it is implemented as the rule-based system in order to represented accurately and effectively the interlocking relationships. Especially in case of emergency the function which determines the rational route coordinating with IIKBAG on the workstation is designed in order to minimize the spreading effect. It is implemented in C computer language for the purpose of the implementation of the inference engine using the dynamic memory allocation technique, the build and interface of the station structure database. And, the validity of the built expert system is proved by simulating the diversity cases which may occur in the real system for the typical station model.

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Conceptual Design of High Speed Data Processing Unit for Next Generation Satellite (차세대 인공위성용 고속데이터 처리유닛 개념설계)

  • Oh, Dae-Soo;Seo, In-Ho;Lee, Jong-Ju;Park, Hong-Young;Chung, Tae-Jin;Kim, Hyung-Myung;Park, Jong-Oh;Yoon, Jong-Jin;Cha, Kyung-Hwan
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.36 no.6
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    • pp.616-620
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    • 2008
  • High reliability is the important parameter on designing satellite system and it is also important to design hish speed data processing unit. To make high speed satellite processing unit, it is needed to utilize space processor, high speed data interface technology, mass memory control technology and data protection technology under space radiation environment.

Location Based Routing Service In Distributed Web Environment

  • Kim, Do-Hyun;Jang, Byung-Tae
    • Proceedings of the KSRS Conference
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    • 2003.11a
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    • pp.340-342
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    • 2003
  • Location based services based on positions of moving objects are expanding the business area gradually. The location is included all estimate position of the future as well as the position of the present and the past. Location based routing service is active business application in which the position information of moving objects is applied efficiently. This service includes the trajectory of past positions, the real-time tracing of present position of special moving objects, and the shortest and optimized paths combined with map information. In this paper, we describes the location based routing services is extend in distributed web GIS environment. Web GIS service systems provide the various GIS services of analyzing and displaying the spatial data with friendly user - interface. That is, we propose the efficient architecture and technologies for servicing the location based routing services in distributed web GIS environment. The position of moving objects is acquired by GPS (Global Positioning System) and converted the coordinate of real world by map matching with geometric information. We suppose the swapping method between main memory and storages to access the quite a number of moving objects. And, the result of location based routing services is wrapped the web-styled data format. We design the schema based on the GML. We design these services as components were developed in object-oriented computing environment, and provide the interoperability, language-independent, easy developing environment as well as re - usability.

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A Case Study on Hardware Trojan: Cache Coherence-Exploiting DoS Attack (하드웨어 Trojan 사례 연구: 캐시 일관성 규약을 악용한 DoS 공격)

  • Kong, Sunhee;Hong, Bo-Uye;Suh, Taeweon
    • Proceedings of the Korea Information Processing Society Conference
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    • 2015.10a
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    • pp.740-743
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    • 2015
  • The increasing complexity of integrated circuits and IP-based hardware designs have created the risk of hardware Trojans. This paper introduces a new type of threat, the coherence-exploiting hardware Trojan. This Trojan can be maliciously implanted in master components in a system, and continuously injects memory read transactions on to bus or main interconnect. The injected traffic forces the eviction of cache lines, taking advantage of cache coherence protocols. This type of Trojans insidiously slows down the system performance, incurring Denial-of-Service (DoS) attack. We used Xilinx Zynq-7000 device to implement and evaluate the coherence-exploiting Trojan. The malicious traffic was injected through the AXI ACP interface in Zynq-7000. Then, we collected the L2 cache eviction statistics with performance counters. The experiment results reveal the severe threats of the Trojan to the system performance.