• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5B
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• pp.899-912
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• 2000

PVM provides users with a single image of high performance parallel computing machine by collecting machines distributed over a network. Low communication overhead is essential to effectively run applications on PVM based platforms. In the original PVM, three times of memory copies are required for a PVM task to send a message to a remote task, which results in performance degradation. We propose a zero-copy model using global shared memory that can be accessed by PVM tasks, PVM daemon, and network interface card(NIC). In the scheme, a task packs data into global shared memory, and notify daemon that the data is ready to be sent, then daemon routes the data to a remote task to which it is sent with no virtual data copy overhead. Experimental result reveals that the message round trip time between two machines is reduced significantly in the proposed zero-copy scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.71-78
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• 2009

An 8${\times}$8-Gb/s/channel 4-PAM transceiver was designed for high speed memory applications by using 70nm DRAM process with 1.35V supply. An asymmetric 4-PAM signaling scheme is proposed to increase the voltage and time margin of upper and lower eyes in 3-class eye opening. A mathematical basis shows that this scheme statistically reduces 33% of reference noise effect in a receiver. Also, an adaptive pre-emphasis scheme, which utilizes a lone-bit pulse with integrator at the receiver, is introduced to reduce ISI for a simple DRAM channel. In this scheme, an integrating clock timing calibration by using a pre-determined pattern is proposed for the optimum ISI measurement.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.6
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• pp.449-453
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• 2010

In this paper, the electrical characteristics of Fin-type SONOS(silicon-oxide-nitride-oxide-silicon) flash memory device with different trapping layers are analyzed in depth. Two kinds of trapping layers i.e., silicon nitride($Si_3N_4$) and hafnium oxide($HfO_2$) are applied. Compared to the conventional Fin-type SONOS device using the $Si_3N_4$ trapping layer, the Fin-type SOHOS(silicon-oxide-high-k-oxide-silicon) device using the $HfO_2$ trapping layer shows superior program/erase speed. However, the data retention properties in SOHOS device are worse than the SONOS flash memory device. Degraded data retention in the SOHOS device may be attributed to the tunneling leakage current induced by interface trap states, which are supported by the subthreshold slope and low frequency noise characteristics.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.1
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• pp.1-7
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• 2000

The SNOSFET memory devices with ultrathin ONO(tunnel oxide-nitride-blocking oxide) gate dielectric were fabricated using n-well CMOS process and investigated its characteristics. The thicknesses of tunnel oxide, nitride and blocking oxide were $23{\AA},\; 53{\AA}\; and\; 33{\AA}$, respectively. Auger analysis shows that the ONO layer is made up of $SiO_2(upper layer of blocking oxide)/O-rich\; SiO_x\N\_y$. It clearly shows that the converting layer with $SiO_x\N\_y(lower layer of blocking oxide)/N-rich SiO_x\N\_y(nitride)/O-rich SiO_x\N\_y(tunnel oxide)$. It clearly shows that the converting layer with $SiO_x\N\_y$ phase exists near the interface between the blocking oxide and nitride. The programming condition of +8 V, 20 ms, -8 V, 50 ms is determined and data retention over 10 years is obtained. Under the condition of 8 V programming, it was confirmed that the modified Fowler-Nordheim tunneling id dominant charge transport mechanism. The programmed threshold voltage is distributed less than 0.1 V so that the reading error of memory stated can be minimized. An $8\times8$ NAND type flash EEPROM with SONOSFET memory cell was designed and simulated with the extracted SPICE parameters. The sufficient read cell current was obtained and the upper limit of $V_{TH}$ for write state was over 2V.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.57-66
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• 2014

This paper presents a low-complexity barrel distortion correction processor for wide-angle cameras. The proposed processor performs the barrel distortion correction jointly with the color demosaicking, so that the hardware complexity can be reduced significantly. In addition, to reduce the required memory bandwidth, an efficient memory interface is proposed by utilizing the spatial locality of the memory access in the correction process. The proposed processor is implemented with 35K logic gates in a $0.11-{\mu}m$ CMOS process and its correction speed is 150 Mpixels/s at the operating frequency of 606MHz, where the supported frame size is $2048{\times}2048$ and the required memory bandwidth is 1 read/cycle.

• Journal of KIISE
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• v.43 no.8
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• pp.841-847
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• 2016

As network technology advances, a larger number of devices are connected through the Internet. Recently, cloud storage services are gaining popularity, as they are convenient to access anytime and anywhere. Among cloud storage services, object storage is the representative one due to their characteristics of low cost, high availability, and high durability. One limitation of object storage services is that they can access data on the cloud only through the HTTP-based RESTful APIs. In our work, we resolve this limitation with the in-memory file system which provides a POSIX interface to the file system users and communicates with cloud object storages with RESTful APIs. In particular, our flush mechanism is compatible with existing file systems, as it is based on the swap mechanism of the Linux kernel. Our in-memory file system backed by cloud storage reduces the performance overheads and shows a better performance than S3QL by 57% in write operations. It also shows a comparable performance to tmpfs in read operations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.369-378
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• 2003

This paper presents design and VLSI implementations of a reassembly processor for ATM/AAL. The assembly processor is responsible for processing ATM cells from the receive physical interface. It controls the transfer of the AAL payload to host memory and performs all necessary SAR and CPCS checks. We propose the improved structure of cell identification algorithm and smart scatter method for host memory management. The proposed cell identification algorithm quickly locates the appropriate reassembly VC table based on the received VPI./VCI channel value in the ATM header. The cell identification algorithm also allow complete freedom in assignment of VCI/VPI values. The reassembly processor uses a smart scatter method to write cell payload data to host memory. It maintains the scatter operation and controls the incoming DMA block during scatter DMA to host memory. The proposed reassembly processor can perform reassembly checks on AAL. OAM cell. For an AAL5 connection, only CPCS checks, including the CRC32, are performed. In this paper, we proposed a practical reassembly architecture. The design of reassembly processor has become feasible using 0.6${\mu}{\textrm}{m}$ CMOS gate array technology.

• The Journal of the Acoustical Society of Korea
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• v.38 no.4
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• pp.433-441
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• 2019

In this paper, a method of estimating speech parameters for ultrasonic Doppler signals reflected from the articulatory muscles using LSTM (Long Short Term Memory) RNN (Recurrent Neural Networks) was introduced and compared with the method using MLP (Multi-Layer Perceptrons). LSTM RNN were used to estimate the Fourier transform coefficients of speech signals from the ultrasonic Doppler signals. The log energy value of the Mel frequency band and the Fourier transform coefficients, which were extracted respectively from the ultrasonic Doppler signal and the speech signal, were used as the input and reference for training LSTM RNN. The performance of LSTM RNN and MLP was evaluated and compared by experiments using test data, and the RMSE (Root Mean Squared Error) was used as a measure. The RMSE of each experiment was 0.5810 and 0.7380, respectively. The difference was about 0.1570, so that it confirmed that the performance of the method using the LSTM RNN was better.

• Journal of IKEEE
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• v.26 no.4
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• pp.659-670
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• 2022

An 830-Mb/s/pin transceiver for a controller supporting ×32 LPDDR2 memory is designed. The transmitter consists of eight unit circuits has an impedance in the range of 34Ω ∽ 240Ω, and its impedance is controlled by an impedance correction circuit. The transmitted DQS signal has a phase shifted by 90° compared to the DQ signals. In the receive operation, the read time calibration is performed by per-pin skew calibration and clock-domain crossing within a byte. The implemented transceiver for the LPDDR2 memory controller is designed by using a 55-nm process using a 1.2V supply voltage and has a maximum signal transmission rate of 830 Mb/s/pin. The area and power consumption of each lane are 0.664 mm² and 22.3 mW, respectively.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.33 no.2
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• pp.345-351
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• 2023

As software development progresses and programs become increasingly complex, the cost of reducing and managing software vulnerabilities has also increased. To address this issue, the Rust programming language, which guarantees Memory Safety, has been suggested as an alternative for more error-prone languages such as traditional C/C++. However, Rust also supports the use of libraries written in C/C++ to enhance compatibility with older languages and avoid redundant development, compromising its original guarantees. For example, memory corruption happened in C/C++ can lead to exploits such as buffer overflow, Use-After-Free and null-pointer dereferecing. To tackle this problem, recent studies have been conducted to secure interactino between Rust and C/C++ by isolation. This paper uncovers areas that have not been fully explored in previous studies, following limitation analysis on each. Finally, this paper suggests the future direction of research on safe interaction between Rust and C/C++.