• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.17-20
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• 2001

Nonvolatile semiconductor memory devices with reoxidized nitrided oxide(RONO) gate dielectrics were fabricated, and nitrogen distribution and bonding species which contribute to memory characteristics were analyzed. Also, memory characteristics of devices depending on the anneal temperatures were investigated. The devices were fabricated by retrograde twin well CMOS processes with $0.35{\mu}m$ Nonvolatile semiconductor memory devices with reoxidized nitrided oxide(RONO) gate dielectric were fabricated, and nitrogen distribution and bonding species which contributing memory characteristics were analyzed. Also, memory characteristics of devices according to anneal temperatures were investigated. The devices were fabricated by $0.35{\mu}m$ retrograde twin well CMOS processes. The processes could be simple by in-situ process of nitridation anneal and reoxidation. The nitrogen distribution and bonding state of gate dielectric were investigated by Dynamic Secondary Ion Mass Spectrometry(D-SIMS), Time-of-Flight Secondary Ion Mass Spectrometry(ToF-SIMS), and X-ray Photoelectron Spectroscopy(XPS). Nitrogen concentrations are proportional to nitridation anneal temperatures and the more time was required to form the same reoxidized layer thickness. ToF-SIMS results show that SiON species are detected at the initial oxide interface and $Si_{2}NO$ species near the new $Si-SiO_{2}$ interface that formed after reoxidation. As the anneal temperatures increased, the device showed worse retention and degradation properties. These could be said that nitrogen concentration near initial interface is limited to a certain quantity, so excess nitrogen are redistributed near the $Si-SiO_{2}$ interface and contributed to electron trap generation.

• The KIPS Transactions:PartA
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• v.11A no.7 s.91
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• pp.475-482
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• 2004

We live in the flood of information due to advancement of information communication and increase of E-mail. Managing users huge in-formation systematically and speedy searching are needed in these social advancement. In this thesis, in order to satisfy these requirement, We suggested Real-time LDAP Interface using Main Memory Resident Database Management System which can manage a lot of information fast systematically. It is expected that system can provide advantage of performance improvement through replacing Main Memory Resident Database Management System without change of application which is required high speed process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.17-20
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• 2001

Nonvolatile semiconductor memory devices with reoxidized nitrided oxide(RONO) gate dielectric were fabricated, and nitrogen distribution and bonding species which contributing memory characteristics were analyzed. Also, memory characteristics of devices according to anneal temperatures were investigated. The devices were fabricated by 0.35$\mu\textrm{m}$ retrograde twin well CMOS processes. The processes could be simple by in-situ process of nitridation anneal and reoxidation. The nitrogen distribution and bonding state of gate dielectric were investigated by Dynamic Secondary Ion Mass Spectrometry(D-SIMS), Time-of-Flight Secondary ton Mass Spectrometry(ToF-SIMS), and X-ray Photoelectron Spectroscopy(XPS). Nitrogen concentrations are proportional to nitridation anneal temperatures and the more time was required to form the same reoxidized layer thickness. ToF-SIMS results show that SiON species are detected at the initial oxide interface and Si$_2$NO species near the new Si-SiO$_2$ interface that formed after reoxidation. As the anneal temperatures increased, the device showed worse retention and degradation properties. These could be said that nitrogen concentration near initial interface is limited to a certain quantity, so excess nitrogen are redistributed near the Si-SiO$_2$ interface and contributed to electron trap generation.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.4
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• pp.32-43
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• 2023

Resistive Random Access Memory (RRAM), based on resistive switching characteristics, is emerging as a next-generation memory device capable of efficiently processing large amounts of data through its fast operation speed, simple device structure, and high-density implementation. Interface type resistive switching offer the advantage of low operation currents without the need for a forming process. Especially, for RRAM devices based on transition metal oxides, various studies are underway to enhance the memory characteristics, including precise material composition control and improving the reliability and stability of the device. In this paper, we introduce various methods, such as doping of heterogeneous elements, formation of multilayer films, chemical composition adjustment, and surface treatment to prevent degradation of interface type resistive switching properties and enhance the device characteristics. Through these approaches, we propose the feasibility of implementing high-efficient next-generation non-volatile memory devices based on improved resistive switching properties.

• Proceedings of the KSRS Conference
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• 2003.11a
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• pp.499-501
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• 2003

As semiconductor memory becomes cheaper, the memory capacity of computer system is increasing. Therefore computer system has sufficient memory for a plentiful spatial data. With emerging spatial application required high performance, this paper presents a GIS database system in main memory. Memory residence can provide both functionality and performance for a database management system. This paper describes design of DBMS for storing, querying, managing and analyzing for spatial and non-spatial data in main-memory. This memory resident GIS DBMS supports SQL for spatial query, spatial data model, spatial index and interface for GIS tool or applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.94-95
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• 2007

In this paper, the dependence of electrical characteristics of Silicon-$Al_2O_3$-Nitride-Oxide-Silicon (SANOS) memory cell transistors and program speed, reliability of memory device on interface trap between Si substrate and tunneling oxide was investigated. The devices were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SONOS cell transistors with larger interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. Therefore, to improve SANOS memory characteristic, it is very important to optimize the interface trap and charge trapping layer.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.12
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• pp.2632-2640
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• 2011

In this paper, we implemented a memory controller which can accommodate data processing blocks. The memory controller is arbitrated by the internal arbiter which receives request signals from masters and sends grant and data signals to masters. The designed memory controller consists of Master Interface, Master Arbitrator, Memory Interface, Memory accelerator. It was designed using VHDL, and verified using the memory model of SAMSING Inc. For FPGA synthesis and verification, Quartus II of ATERA Inc. was used. The target device is Cyclone II. For simulation, ModelSim of Cadence Inc was used.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2004.04a
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• pp.389-395
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• 2004

We consider the interface between the parallel distributed memory multifrontal solver and the finite element method. We give in detail the requirement and the data structure of parallel FEM interface which includes the element data and the node array. The full procedures of solving a large scale structural problem are assumed to have pre-post processors, of which algorithm is not considered in this paper. The main advantage of implementing the parallel FEM interface is shown up in the case that we use a distributed memory system with a large number of processors to solve a very large scale problem. The memory efficiency and the performance effect are examined by analyzing some examples on the Pegasus cluster system.

• Electrical & Electronic Materials
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• v.8 no.6
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• pp.727-736
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• 1995

This paper examines the characteristics and physical properties of the scaled MONOS nonvolatile memory device for low programming voltage EEPROM. The capacitor-type MONOS memory devices with the nitride thicknesses ranging from 41.angs. to 600.angs. have been fabricated. As a result, the 5V-programmable MONOS device has been obtained with a 20ms programming time by scaling the nitride thickness to 57.angs. with a tunneling oxide thickness of 19.angs. and a blocking oxide thickness of 20.angs.. Measurement results of the quasi-static C-V curves indicate, after 10$\^$6/ write/erase cycles, that the devices are degraded due to the increase of the silicon-tunneling oxide interface traps. The 10-year retention is impossible for the device with a nitride less than 129.angs.. However, the MONOS memory device with 10-year retentivity has been obtained by increasing the blocking oxide thickness to 47.angs.. Also, the memory traps such as the nitride bulk trap and the blocking oxide-nitride interface trap have been investigated by measuring the maximum flatband voltage shift and analyzing through the best fitting method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.360-369
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• 2012

The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NAND flash memory with planar structure were investigated. To analyze the difference in SSs, TCAD simulation and low-frequency noise (LFN) measurement were fulfilled. The device simulation was performed to compare SSs considering the gate electric field effect to the channel and to check the localized trapped charge distribution effect in nitride layer while the comparison of noise power spectrum was carried out to inspect the generation of interface traps ($N_{IT}$). When each cell in the measured two memory devices is erased, the normalized LFN power is increased by one order of magnitude, which is attributed to the generation of $N_{IT}$ originated by the movement of hydrogen species ($h^*$) from the interface. As a result, the SS is degraded for the GAA SONOS memory device when erased where the $N_{IT}$ generation is a prominent factor. However, the TANOS memory cell is relatively immune to the SS degradation effect induced by the generated $N_{IT}$.