• Proceedings of the KIEE Conference
• /
• 1988.07a
• /
• pp.247-249
• /
• 1988

The most space-consuming element of digital image processing system is the video memory. Though this problem is solved by DRAMs, timing constraints posed by video data rates. The cycle time of DRAMs can be diminished by serial transferring and reading or writing pixel datas at the same time. This paper resents the design of 1024${\times}$512 video memory using this technique.

• Proceedings of the KIEE Conference
• /
• 1988.07a
• /
• pp.567-570
• /
• 1988

This paper describes the design of FIR filtering DSP-chip that can be operated without programming. The proposed DSP-chip has not only the improvement of execution time but also selectivity of filter length from N=1 to N=128. Hilbert Transformer can be designed from this chip. FIR filter system is composed of Data memory/Control Unit, external memory and multiplier-accumulator. Data memory/Control Unit is laid out in this paper.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2001.10a
• /
• pp.567-570
• /
• 2001

In this paper, we proposed flash memory design method for image and voice recoder based on the standard imageㆍvoice codec algorithm. For implementation of this method we designed image voice browser which is application system of flash memory and card using GDS30C6001 USB controller. To process image and voice data we designed root directory of image and voice files repectively. To extend application of image and voice data we added various information to the system.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.24 no.6B
• /
• pp.1183-1190
• /
• 1999

This paper presents an efficient hardware architecture to improve the frame memory interface occupying the largest hardware area together with motion estimator in implementing MPEG-2 video encoder as an ASIC chip. In this architecture, the memory size for internal data buffering and hardware area for frame memory interface control logic are reduced through the efficient memory map organization of the external SDRAM having dual bank and memory access timing optimization between the video encoder and external SDRAM. In this design, 0.5 m, CMOS, TLM (Triple Layer Metal) standard cells are used as design libraries and VHDL simulator and logic synthesis tools are used for hardware design add verification. The hardware emulator modeled by C-language is exploited for various test vector generation and functional verification. The architecture of the improved frame memory interface occupies about 58% less hardware area than the existing architecture[2-3], and it results in the total hardware area reduction up to 24.3%. Thus, the (act that the frame memory interface influences on the whole area of the video encoder severely is presented as a result.

• Journal of the Microelectronics and Packaging Society
• /
• v.24 no.4
• /
• pp.91-95
• /
• 2017

Package-On-Package (PoP) technology is developing toward smaller form factors with high-speed data transfer capabilities to cope with high DDR4x memory capacity. The common application processor (AP) used for PoP devices in smartphones has the bottom package as logic and the top package as memory, which requires both thermally and electrically enhanced functions. Therefore, it is imperative that PoP designs consider both thermal and power distribution network (PDN) issues. Stacked packages have poorer thermal dissipation than single packages. Since the bottom package usually has higher power consumption than the top package, the bottom package impacts the thermal budget of the top package (memory). This paper investigates the thermal and electrical characteristics of PoP designs, particularly the bottom package. Findings include that via and dense via-cluster volume have an important role to lower thermal resistance to the motherboard, which can be an effective way to manage chip hot spots and reduce the thermal impact on the memory package. A Cu block and dense via-cluster layout with an optimal location are proposed to drain the heat from the chip hot spots to motherboard which will enhance thermal and electrical performance at the design stage. The analytical thermal results can be used for design guidelines in 3D packaging.

• Journal of electromagnetic engineering and science
• /
• v.9 no.2
• /
• pp.71-77
• /
• 2009

OFDM(Orthogonal Frequency Division Multiplexing) signals sutler serious nonlinear distortion in the nonlinear HPA(High Power Amplifier) because of high PAPR(Peak Average Power Ratio). Nonlinear distortion can be improved by a pre-distorter, but this pre-distorter is insufficient when the PAPR is very high in an OPFDM system. In this paper, a DFT(Discrete Fourier Transform) transform technique is introduced for PAPR reduction. It is especially important to consider the memory effect of HPA for more precise predistortion. Therefore, in this paper, we consider two models, the TWTA(Traveling-Wave Tube Amplifier) model of Saleh without a memory effect and the HPA memory polynomial model that has a memory effect. We design a pre-distorter and an adaptive pre-distorter that uses the NLMS(Normalized Least Mean Square) algorithm for the compensation of this nonlinear distortion. Without the consideration of a memory effect, the system performance would be degraded, even if the pre-distorter is used for the compensation of the nonlinear distortion. From the simulation results, we can confirm that the proposed system shows an improvement in performance.

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.719-722
• /
• 1998

Fault simulation for large and complex sequential circuits is highly cpu-intensive task in the intergrated circuit design process. In this paper, we propose CM-SIM, a concurrent fault simulator which employs an optimal memory management strategy and simple list operations. CM-SIM removes inefficiencies and uses new dynamic memory management strategies, using contiguous array memory. Consequently, we got improved performance and reduced memory usage in concurrent fault simulation.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.6
• /
• pp.963-971
• /
• 1990

This paper proposes a memory intensive VLSI architecture for the realization of real-time 3x3 neighborhood processor based on the distributed arithmetic. The proposed architecture is characterized by a bit serial and multi-kernel parallel processing which exploits the pixel kernel parallelism and concurrency. The chip implements 8 neighborhood processing elements in parallel with efficirnt input and output modules which operate concurrently. Besides the a4chitectural design of a neighborhood processor, the design methodology using module generator concept has been considered and MOGOT(MOdule Generator Oriented VLSI design Tool) has been constructed based on the workstation. Based on these design environments MOGOT, it has been shown that the main part of the suggested architecture can be designed efficiently using 2\ulcorner double metal CMOS technology. It includes design of input delay and data conversion module, look-up table for inner product operation, carry save accumulator, output data converter and delay module, and control module.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.3 no.2
• /
• pp.79-85
• /
• 2008

It is important to consider the life of battery and low power operation for various wireless communications. Thus, Analog current-mode signal processing with SI circuit has been taken notice of in designing the LSI for wireless communications. However, in current mode signal processsing, current memory circuit has a problem called clock-feedthrough. In this paper, we examine the connection of CMOS switch that is the common solution of clock-feedthrough and calculate the relation of width between CMOS switch for design methodology for improvement of current memory. As a result of simulation, when the width of memory MOS is 20um, ratio of input current and bias current is 0.3, the width relation in CMOS switch is obtained with $W_{Mp}=5.62W_{Mn}+1.6$, for the nMOS width of 2~6um in CMOS switch. And from the same simulation condition, it is obtained with $W_{Mp}=2.05W_{Mn}+23$ for the nMOS width of 6~10um in CMOS switch. Then the defined width relation of MOS transistor will be useful guidance in design for improvement of current memory.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.5 no.2
• /
• pp.77-83
• /
• 2010

In this paper, we propose an efficient memory architecture for coeff_token encoding in H.264/AVC standard. The VLCTs used to encode the coeff_token syntax element are implemented with the memory. In general, the size of memory must be reduced because it affects the cost and operation speed of the system. Based on the analysis for the codewords in VLCTs, new memory architecture is designed in this paper. The proposed memory architecture results in about 24% memory saving, compared to the conventional memory architecture.