• Smart Structures and Systems
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• v.31 no.1
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• pp.45-56
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• 2023

Vibration-based structural health monitoring is used to ensure the safety of structures by installing sensors in structures. The peak picking method, one of the applications of vibration-based structural health monitoring, is a method that analyze the dynamic characteristics of a structure using the peaks of the frequency response function. However, the results may vary depending on the person predicting the peak point; further, the method does not predict the exact peak point in the presence of noise. To overcome the limitations of the existing peak picking methods, this study proposes a new method to automate the modal analysis process by utilizing long short-term memory, a type of recurrent neural network. The method proposed in this study uses the time series data of the frequency response function directly as the input of the LSTM network. In addition, the proposed method improved the accuracy by using the phase as well as amplitude information of the frequency response function. Simulation experiments and lab-scale model experiments are performed to verify the performance of the LSTM network developed in this study. The result reported a modal assurance criterion of 0.8107, and it is expected that the dynamic characteristics of a civil structure can be predicted with high accuracy using data without experts.

• Communications for Statistical Applications and Methods
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• v.31 no.2
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• pp.213-234
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• 2024

In recent decades, increasing research attention has been directed toward predicting the price of stocks in financial markets using deep learning methods. For instance, recurrent neural network (RNN) is known to be competitive for datasets with time-series data. Long short term memory (LSTM) further improves RNN by providing an alternative approach to the gradient loss problem. LSTM has its own advantage in predictive accuracy by retaining memory for a longer time. In this paper, we combine both supervised and unsupervised dimension reduction methods with LSTM to enhance the forecasting performance and refer to this as a dimension reduction based LSTM (DR-LSTM) approach. For a supervised dimension reduction method, we use methods such as sliced inverse regression (SIR), sparse SIR, and kernel SIR. Furthermore, principal component analysis (PCA), sparse PCA, and kernel PCA are used as unsupervised dimension reduction methods. Using datasets of real stock market index (S&P 500, STOXX Europe 600, and KOSPI), we present a comparative study on predictive accuracy between six DR-LSTM methods and time series modeling.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.8
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• pp.399-403
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• 2006

An accurate constant output voltage provided by the analog memory cell may be used by the low power oscillator to generate an accurate low frequency output signal. This accurate low frequency output signal may be used to maintain long-term timing accuracy in host devices during sleep modes of operation when an external crystal is not available to provide a clock signal. Further, incorporation of the analog memory cell in the low power oscillator is fully implementable in a 0.35um Samsung standard CMOS process. Therefore, the analog memory cell incorporated into the low power oscillator avoids the previous problems in a oscillator by providing a temperature-stable, low power consumption, size-efficient method for generating an accurate reference clock signal that can be used to support long sleep mode operation.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1571-1574
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• 2002

This paper describes a circuit and its operations of a programmable digital on-chip terminator designed with CMOS circuits which are used in high speed I/O interface. The on-chip terminator matches external reference resistor with the accuracy of ${\pm}$ 4.1％ over process, voltage and temperature variation. The digital impedance codes are generated in programmable impedance controller (PIC), and the codes are sent to terminator transistor arrays at input pads serially to reduce the number of signal lines. The transistor array is thermometer-coded to reduce impedance glitches during code update and it is segmented to two different blocks of thermometer-coded transistor arrays to reduce the number of transistors. The terminator impedance is periodically updated during hold time to minimize inter-symbol interferences.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.6
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• pp.425-432
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• 2004

In this paper, we introduce the analog memory fabricated in a 0.35${\mu}{\textrm}{m}$ single poly standard CMOS process. We measured the programming characteristics of the analog memory cell such as linearity, reliability etc. Finally, we found that the characteristics of the programming of the cell depend on the magnitude and the width of the programming pulse, and that the accuracy of the programming within 10mV is feasible under the optimal condition. In order to standardize the characteristics of the cell, we have investigated numbers of cells. Thus we have used a program named Labview and a data acquisition board to accumulate the data related to the programming characteristics automatically.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.2
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• pp.38-45
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• 2014

This paper proposes a characterization method based on the reference memory to characterize memory compiler quickly and accurately. In order to maintain the accuracy of the memory complier and to minimize characterization time, the proposed method models the trends of the generated memories by selecting the reference memories after analyzing the timing trends of the memory compiler. To validate the proposed method, we characterized the 110nm memory compiler derived from 130nm memroy compiler. The average error rate of the characteristics of the memories generated by the proposed method and SPICE simulation is lower than ${\pm}0.1%$. Furthermore, we designed memory BIST test chips at 110nm and 180nm processes and the results of the function test show that the yield is 98.8% and 98.3%, respectively. Therefore, the proposed method is useful to characterize the memory compiler.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.6
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• pp.2497-2517
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• 2020

For compressed sensing (CS) applications, it is significant to construct deterministic measurement matrices with good practical features, including good sensing performance, low memory cost, low computational complexity and easy hardware implementation. In this paper, a deterministic construction method of bipolar measurement matrices is presented based on binary sequence family (BSF). This method is of interest to be applied for sparse signal restore and image block CS. Coherence is an important tool to describe and compare the performance of various sensing matrices. Lower coherence implies higher reconstruction accuracy. The coherence of proposed measurement matrices is analyzed and derived to be smaller than the corresponding Gaussian and Bernoulli random matrices. Simulation experiments show that the proposed matrices outperform the corresponding Gaussian, Bernoulli, binary and chaotic bipolar matrices in reconstruction accuracy. Meanwhile, the proposed matrices can reduce the reconstruction time compared with their Gaussian counterpart. Moreover, the proposed matrices are very efficient for sensing performance, memory, complexity and hardware realization, which is beneficial to practical CS.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.10
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• pp.4098-4116
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• 2020

Mobile devices such as smartphones are very attractive targets for augmented reality (AR) services, but their limited resources make it difficult to increase the number of objects to be recognized. When the recognition process is scaled to a large number of objects, it typically requires significant computation time and memory. Therefore, most large-scale mobile AR systems rely on a server to outsource recognition process to a high-performance PC, but this limits the scenarios available in the AR services. As a part of realizing large-scale standalone mobile AR, this paper presents a solution to the problem of accuracy, memory, and speed for large-scale object recognition. To this end, we design our own basic feature and realize spatial locality, selective feature extraction, rough pose estimation, and selective feature matching. Experiments are performed to verify the appropriateness of the proposed method for realizing large-scale standalone mobile AR in terms of efficiency and accuracy.

• Proceedings of the KIEE Conference
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• 2001.07e
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• pp.134-140
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• 2001

Parallel processing has the potential to be cost effectively used on computationally intense power system problems. But this technology is not still available is not only parallel computer but also parallel processing scheme. Testing these algorithms to ensure accuracy, and evaluation of their performance is also an issue. Although a significant amount of parallel algorithms of power system problem have been developed in last decade, actual testing on processor architectures lies in the beginning stages. This paper presents the parallel processing algorithm to supply the base being able to treat power flow by newton's method by the distributed memory type parallel computer. This method is to assign and to compute teared blocks of sparse matrix at each parallel processors. The testing to insure accuracy of developed method have been done on serial computer by trying to simulate a parallel environment.

• The Korean Journal of Legal Medicine
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• v.39 no.4
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• pp.115-119
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• 2015

We investigated event-related potentials (ERPs) to estimate the accuracy of eyewitness memories. Participants watched videos of vehicles being driven dangerously, from an anti-impaired driving initiative. The four-letter license plates of the vehicles were the target stimuli. Random numbers were presented while participants attempted to identify the license plate letters, and electroencephalograms were recorded. There was a significant difference in activity 300-500 milliseconds after stimulus onset, between target stimuli and random numbers. This finding contributes to establishing an eyewitness recognition model where different ERP components may reflect more explicit memory that is dissociable from recollection.