• IE interfaces
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• v.21 no.1
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• pp.131-140
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• 2008

To shorten product development time and cost, integrated information managements of product, manufacturing process and resource are essential. In the area of material addressing, process engineers should make their decisions in the manner of collaborative engineering in order to reduce the manufacturing preparation time and cost in the product development and production. A digital virtual factory which is an united digital model of entire factory could be very useful for these areas. In this paper, the digital virtual factory is constructed and used for material addressing and analysis of an automotive general assembly shop. We developed the material addressing system for automotive general assembly shops using digital virtual factory models and nesting algorithms, and applied it to realistic problems of a Korean automotive company as an convenient and effective way of material addressing.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.08a
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• pp.67-71
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• 2003

One of the most important problems in ADS method is that the method has too long addressing period, The addressing time can be defined as the sum of the discharge time lag and the duration of discharge current. If the addressing time increases, the sustaining period for display image should be decreased. As a result, the luminance of the PDP decreases. Therefore, the discharge time lag and duration of discharge current should be decreased in order to reduce the addressing time. In this paper, in order to improve addressing time, relationships between addressing time and cell structure in AC PDP was studied

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.12
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• pp.1065-1069
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• 2002

The addressing time should be reduced by modifying cell structure and/or driving method in order to replace the dual scan system by single scan and increase the luminance in large ac plasma display panel(PDP). In this paper, the effects of the addressing time was decreased with decreasing thickness of dielectric layer on the front glass and thickness of white dielectric layer on the rear glass. the decreasing rate were 160ns/10$\mu\textrm{m}$ and 270ns/10$\mu\textrm{m}$, respectively Also in case of decreasing the height of barrier rib, addressing time was decreased at the rate of Sons/10$\mu\textrm{m}$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.120-123
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• 2000

Bridge Type Cell structure informed that the efficiency is increased by about 30% compared to the conventional type has been investigated during addressing period. As a result, the addressing time is decreased by about 20% compared to the conventional type. And wall charge distribution was analyzed Quantitatively in three electrodes during addressing period.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.1
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• pp.63-67
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• 2008

The charged particle type display is a kind of electronic paper showing information images using positive and negative charged particles ($<10{\mu}m$). In this work we used yellow(-) and black(+) particles which are respectively addressed to the cells of a upper and a rear substrate by using electric field. Our independent addressing method has strong points compared to the mixed particle putting method. The packaging with two orthogonal substrates and the aging process is followed by addressing process. The panel is sequentially driven by matrix method for each 4-unit cells. Layers of particles are controlled by barrier ribs and must be addressed to minimum 2 layers.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.391-394
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• 1999

Until now, there is no report for the relationship between the condition of addressing and the characteristics of surface discharge in ac-PDP. We have known that such these experiment was important to drive ac PDP Therefore, this paper deals with the probability of transfer and the character of luminance according to addressing voltage(Va) and blocking voltage(Vg) in addressing period and sustain voltage in sustaining period and we use waveform according to ADS(Address and Display period Separation) method

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.2
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• pp.180-186
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• 2005

As a driving method of AC-PDP, Address-Display Separated(ADS) driving has been widely adopted for its simple architecture and low discharge failure rate. However, a high definition like a HDTV has defect of long addressing time by reason of a number of pixels. Priming effect isn't fully sustained because of long addressing time during the address period. Therefore, it has different wall charge and luminance of each addressing time in the sustain period. In this study, we suggest a new driving waveform on the address period to improve these defects. We applied a ramp waveform, instead of a square waveform, to an address period in ADS, for operating on the AC-PDP, which used the conventional gas [He-Ne-Xe]. When the ramp waveform is applied to the address period, we experimented for uniform wall charge and the improved luminance by sustained Priming effect at each addressing time in the sustain period.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.103-107
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• 2000

The relationships between driving voltage and the wall charge distribution in the address period of surface discharge type AC Plasma Display Panel have been investigated. The quantity of wall charge on each electrode are detected simultaneously from the electrode current after applying only one addressing discharge pulse. The wall charge Qy on the scan electrode Y is nearly the sum of Qx on the address electrode X and Qz on the sustain electrode Z. The Qy increased with the driving voltage regardless of the kind of electrode, whereas the address time Td decreased, Qz and Qy are increased considerably with the blocking voltage Vz, whereas Qx is decreased. The increase rate of Qx, Qy and Qz for increase in Vz was $-13{\times}10^{-2}$ (pc/Vz), and $60{\times}10^{-2}$ (pc/Vz) and $70{\times}10^{-2}$(pc/Vz), respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.112-116
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• 2000

In this paper, we investigated the relationship between the position of bus electrode and address time, luminance and luminous efficiency in ac PDP of 50in. XGA resolution. When the bus electrode was placed in which was about $140{\mu}m$ apart from discharge gap, the luminous efficiency was the highest and address time was the least. Whereas, when the bus electrode was placed in the edge of ITO, the luminance was the highest.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05a
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• pp.149-152
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• 2002

If the ambient temperature rises for AC PDP, some of the discharge cells are turned off because of the misfiring during address period. Particularly, the misfiring of the 'last scan line is more serious than that of the first. In order to compensate the misfiring in such that case, different addressing voltage is applied at each cell such as progressively increasing pulse voltage instead of constant one. As a result, the addressing time and discharge charge of the last scan line have become similar to those of the first scan line and the phenomenon of misfiring has disappeared.