• Title/Summary/Keyword: mapping size

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Topographic mapping using digital map Ver.2.0 (수치지도 Ver.2.0을 이용한 종이지도제작기법 개발)

  • 황창섭;정성혁;함창학;이재기
    • Proceedings of the Korean Society of Surveying, Geodesy, Photogrammetry, and Cartography Conference
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    • 2003.10a
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    • pp.281-286
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    • 2003
  • Since National Geographic Information System was started, paper maps have been made with computer aided editing of digital map, instead of etching map-size negative film. Automated paper mapping system's necessity is growing more and more, because digital map has changed into Ver.2.0 which include attributes of feature. Therefore, in this study we try to analyze correlation of the digital map feature code and the 1/5,000 topographic map specifications which is necessary for paper mapping automatization using digital map Ver.2.0, and try to develop fundamental modules which will play a core role in automated paper mapping system.

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Development of Digital map Ver.2.0 representation conversion system for 1/5,000 Topographic mapping (1/5,000 지형도제작을 위한 수치지도 Ver.2.0 자료변환 시스템 개발)

  • 황창섭;이재기
    • Proceedings of the Korean Society of Surveying, Geodesy, Photogrammetry, and Cartography Conference
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    • 2004.04a
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    • pp.321-328
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    • 2004
  • Since National Geographic Information System was started, topographic maps have been made with computer aided editing of digital map, instead of etching map-size negative film. topographic mapping system's necessity is growing more and more, because digital map has changed into Ver.2.0 which include attributes of feature. On the basis of the previous study for analyzing correlation between the digital map feature code and the 1/5,000 topographic map specifications and trying to develop fundamental modules which will play a core role in topographic mapping system, in this study, we apply some 1/5,000 digital maps Ver.2.0 to topographic mapping system have implemented and try to analyze the result.

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A Wall-Following Method of Mobile Robot for Mapping (Mapping을 위한 자율이동로붓의 Wall Following 기법)

  • Lee, Kang-Min;Lim, Dong-Kyun;Kim, Hyung-Geun;Suh, Byung-Suhl
    • Proceedings of the KIEE Conference
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    • 2005.05a
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    • pp.102-105
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    • 2005
  • A Effective wall following plays important role for the mapping behaviors which determine the entire memory size and the shape of map before building a map. In case of wall following, attacking those cause by curved wall or obstacles brings a bad stuff that makes ripples on the moving trajectory. These types of ripples come to an end with problems that increase the load of calculation and sensing errors. In this paper, a new sensing method and its corresponding controller are suggested for problems. It minimizes the occurrence of the trajectory ripples.

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Domestic Trend Analysis of Mobile Mapping System through Geospatial Information Market and Patent Survey (공간정보 시장과 특허 조사를 통한 국내 Mobile Mapping System 동향 분석)

  • Park, Hong Gi
    • Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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    • v.35 no.6
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    • pp.495-508
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    • 2017
  • Today, MMS (Mobile Mapping System) uses the strengths of individual sensor technologies on a variety of platforms to increase the efficiency of geospatial data collection. In this paper, we analyzed the market size and technology trend of mobile mapping market in Korea and abroad, and analyzed frequency, trend, and characteristics of MMS related patents. The results of the analysis are as follows: First, it is expected that the domestic and overseas mobile mapping market will continue to grow in the future, and MMS-related technologies and applications are rapidly developing. Active research and development investment is required to preoccupy future market through technology development and patent competition. Second, the frequency of filing domestic patents is highly correlated with the results of national R&D, and industrial patent applications are highly related to national projects. It is analyzed as the result of introduction of preemptive technologies and research and development of companies for preemption in related industry rather than market development. Lastly, in Korean geospatial information industry survey, It is necessary to maintain the data so that it can be compared with the data of foreign institutions. In particular, statistical data that can grasp the market size in terms of geospatial information utilization and technical aspects are desperately needed.

Power-Efficient DCNN Accelerator Mapping Convolutional Operation with 1-D PE Array (1-D PE 어레이로 컨볼루션 연산을 수행하는 저전력 DCNN 가속기)

  • Lee, Jeonghyeok;Han, Sangwook;Choi, Seungwon
    • Journal of Korea Society of Digital Industry and Information Management
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    • v.18 no.2
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    • pp.17-26
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    • 2022
  • In this paper, we propose a novel method of performing convolutional operations on a 2-D Processing Element(PE) array. The conventional method [1] of mapping the convolutional operation using the 2-D PE array lacks flexibility and provides low utilization of PEs. However, by mapping a convolutional operation from a 2-D PE array to a 1-D PE array, the proposed method can increase the number and utilization of active PEs. Consequently, the throughput of the proposed Deep Convolutional Neural Network(DCNN) accelerator can be increased significantly. Furthermore, the power consumption for the transmission of weights between PEs can be saved. Based on the simulation results, the performance of the proposed method provides approximately 4.55%, 13.7%, and 2.27% throughput gains for each of the convolutional layers of AlexNet, VGG16, and ResNet50 using the DCNN accelerator with a (weights size) x (output data size) 2-D PE array compared to the conventional method. Additionally the proposed method provides approximately 63.21%, 52.46%, and 39.23% power savings.

A design and implementation of VHDL-to-C mapping in the VHDL compiler back-end (VHDL 컴파일러 후반부의 VHDL-to-C 사상에 관한 설계 및 구현)

  • 공진흥;고형일
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.12
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    • pp.1-12
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    • 1998
  • In this paper, a design and implementation of VHDL-to-C mapping in the VHDL compiler back-end is described. The analyzed data in an intermediate format(IF), produced by the compiler front-end, is transformed into a C-code model of VHDL semantics by the VHDL-to-C mapper. The C-code model for VHDL semantics is based on a functional template, including declaration, elaboration, initialization and execution parts. The mapping is carried out by utilizing C mapping templates of 129 types classified by mapping units and functional semantics, and iterative algorithms, which are combined with terminal information, to produce C codes. In order to generate the C program, the C codes are output to the functional template either directly or by combining the higher mapping result with intermediate mapping codes in the data queue. In experiments, it is shown that the VHDL-to-C mapper could completely deal with the VHDL analyzed programs from the compiler front-end, which deal with about 96% of major VHDL syntactic programs in the Validation Suite. As for the performance, it is found that the code size of VHDL-to-C is less than that of interpreter and worse than direct code compiler of which generated code is increased more rapidly with the size of VHDL design, and that the VHDL-to-C timing overhead is needed to be improved by the optimized implementation of mapping mechanism.

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Efficient IFFT Design Using Mapping Method (Mapping 기법을 이용한 효율적인 IFFT 설계)

  • Jang, In-Gul;Kim, Yong-Eun;Chung, Jin-Gyun
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.44 no.11
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    • pp.11-18
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    • 2007
  • FFT(Fast Fourier Transform) processor is one of the key components in the implementation of OFDM systems such as WiBro, DAB and UWB systems. Most of the researches on the implementation of FFT processors have focused on reducing the complexities of multipliers, memory and control circuits. In this paper, to reduce the memory size required for IFFT(Inverse Fast Fourier Transform), we propose a new IFFT design method based on a mapping method. By simulations, it is shown that the reposed IFFT design method achieves more than 60% area reduction and much SQNR(Signal-to-Quantization-Noise Ratio) gain compared with previous IFFT circuits.

A Study on the Hybrid Fractal clustering Algorithm with SOFM vector Quantizer (벡터양자화기와 혼합된 프렉탈의 클러스터링 알고리즘에 대한 연구)

  • 김영정;박원우;김상희;임재권
    • Proceedings of the IEEK Conference
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    • 2000.11d
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    • pp.195-198
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    • 2000
  • Fractal image compression can reduce the size of image data by contractive mapping of original image. The mapping is affine transformation to find the block(called range block) which is the most similar to the original image. Fractal is very efficient way to reduce the data size. However, it has high distortion rate and requires long encoding time. In this paper, we present the simulation result of fractal and VQ hybrid systems which use different clustering algorithms, normal and improved competitive learning SOFM. The simulation results showed that the VQ hybrid fractal using improved competitive learning SOFM has better distortion rate than the VQ hybrid fractal using normal SOFM.

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A Study on the Hybrid Fractal clustering Algorithm with SOFM vector Quantizer (신경망이 벡터양자화와 프랙탈 혼합시스템에 미치는 영향)

  • 김영정;박원우;김상희;임재권
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 2000.11a
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    • pp.81-84
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    • 2000
  • Fractal image compression can reduce the size of image data by contractive mapping of original image. The mapping is affine transformation to find the block(called range block) which is the most similar to the original image. Fractal is very efficient way to reduce the data size. However, it has high distortion rate and requires long encoding time. In this paper, we present the simulation result of fractal and VQ hybrid systems which use different clustering algorithms, normal and improved competitive learning SOFM. The simulation results showed that the VQ hybrid fractal using improved competitive learning SOFM has better distortion rate than the VQ hybrid fractal using normal SOFM.

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Sub-Micrometer-Sized Spectrometer by Using Plasmonic Tapered Channel-Waveguide

  • Lee, Da Eun;Lee, Tae-Woo;Kwon, Soon-Hong
    • Journal of the Optical Society of Korea
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    • v.18 no.6
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    • pp.788-792
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    • 2014
  • It has been a critical issue to reduce the size of spectrometers in many fields such as on-chip chemical and biological sensing. The proposed plasmonic channel-waveguide with a sub-micrometer width has a cutoff frequency which enables us to control wavelength dependent propagation properties. We focused on the capability of the waveguide for spectral-to-spatial mapping when the waveguide width changes gradually. In this paper, we propose a plasmonic tapered channel-waveguide structure as a compact spectrometer with a physical size of $0.24{\times}2.0{\times}0.20{\mu}m^3$. The scattering point just above the tapered waveguide moves linearly depending on the wavelength of the injecting light. The spectral-to-spatial mapping can be improved by increasing the tapered length.