• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.79-82
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• 2003

This paper describes a new low-swing inverter for low power consumption. To reduce a power consumption, an output voltage swing is in the range from 0 to $V_{ref}-V_{TH}$, where $V_{ref}=V_{DD}-nV_{TH}$. This can be done by the inverter structure that allow a full swing or a swing on its input terminal without leakage current. Using this low-swing voltage technology, we propose a low-power $4\times4$ bit parallel multiplier. The proposed circuits are simulated with HSPICE under $0.35{\mu}m$ CMOS standard technology. Compare to the previous works, this circuit can reduce the power consumption rate of 11.2% and the power-delay product of 10.3%.

• The KIPS Transactions:PartA
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• v.14A no.3 s.107
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• pp.147-150
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• 2007

This paper describes a new low-swing inverter for low power consumption. To reduce a power consumption, an output voltage swing is in the range from 0 to VDD-2VTH. This can be done by the inverter structure that allow a full swing or a swing on its input terminal without leakage current. Using this low-swing voltage technology, we proposed a low-power 16$\times$16 bit parallel multiplier. The proposed circuits are designed with Samsung 0.35$\mu$m standard CMOS process at a 3.3V supply voltage. The validity and effectiveness are verified through the HSPICE simulation.. Compared to the previous works, this circuit can reduce the power consumption rate of 17.3% and the power-delay product of 16.5%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.56-62
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• 2002

A new high speed and low voltage swing on-chip BUS using threshold voltage swing driver and dual sense amplifier receiver is proposed. The threshold voltage swing driver reduces the rising time in the bus to 30% of the full CMOS inverter driver and the dual sense amplifier receiver increases twice the throughput. of the conventional reduced-swing buses using sense amplifier receiver. With threshold voltage swing driver and dual sense amplifier receiver combined, approximately 60% speed improvement and 75% power reduction are achieved in the proposed scheme compared to the conventional full CMOS inverter for the on-chip bus.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.104-109
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• 2009

At a lower supply voltage, voltage-mode drivers draw less current than current-mode drivers. In this paper, we newly propose a voltage-mode driver with an additional current path that reduces the output voltage swing without the need for complicated additional circuitry, compared to conventional voltage-mode drivers. The prototype driver is fabriccated in a 0.13-$^{\mu}m$ CMOS technology and used to transmit data streams at the rate of 2.5 Gb/s. Deemphasis is also implemented for the compensation of channel attenuation. With a 1.2-V supply, it dissipates 8.0 mA for a 400-mV output voltage swing.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.525-526
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• 2008

This paper proposes a new high-speed level shifter using a special high voltage device with low threshold voltage. Also, novel low voltage swing method is proposed. The high voltage device is a standard LDMOS(Laterally Diffused MOS) device in a $0.18{\mu}m$ CMOS process without adding extra mask or process step to realize it. A level shifter uses 5V LDMOSs as voltage clamps to protect 1.8V NMOS switches from high voltage stress the gate oxide. Also, level-up transition from 1.8V to 5V takes only 1.5ns in time. These circuits do not consume static DC power, therefore they are very suitable for low-power and high-speed interfaces in the deep sub-quarter-micron CMOS technologies.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.7
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• pp.10-16
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• 1999

This paper describes a low voltage swing bus driver using FCSR(Feedback Control Swing voltage Reduction) which can control bus swing voltage within a few hundred of mV. It is proposed to reduce power consumption in On-chip interface, especially for MDL(Merged DRAM Logic) architecture wihich has wide and large capacitance bus. FCSR operates on differential signal dual-line bus and on precharged bus with block controlling fuction. We modeled driver and bus to scale driver size automatically when bus environment is variant. We also modeled coupling capacitance noise(crosstalk) of neighborhood lines which operate on odd mode with parallel current source to analysis crosstalk effect in the victim-line according as voltage transition in the aggressor-line and environment in the victim-line. We built a test chip which was designed to swing 600mV in bus, shows 70Mhz operation at 3.3V, using Hyundai 0.8um CMOS technology. FCSR operate with 250Mhz at 3.3V by Hspice simulation.

• Proceedings of the Polymer Society of Korea Conference
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• 2006.10a
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• pp.170-170
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• 2006

[ ${\pi}-conjugated$ ] organic and polymeric semiconductors are receiving considerable attention because of their suitability as an active layer for electronic devices. An organic inverter with a full swing and a high gain can be obtained through the good qualities of the transfer characteristics of organic thin-film transistors (OTFTs); for example, a low leakage current, a threshold voltage ($V_{th}$) close to 0 V, and a low sub-threshold swing. One of the most critical problems with traditional organic inverters is the high operating voltage, which is often greater than 20 V. The high operating voltage may result in not only high power consumption but also device instabilities such as hysteresis and a shift of $V_{th}$ during operation. In this paper, low-voltage and little-hysteresis pentacene OTFTs and inverters in conjunction with PEALD $Al_{2}O_{3}\;and\;ZrO_{2}$ as the gate dielectrics are demonstrated and the relationships between the transfer characteristics of OTFT and the voltage transfer characteristics (VTCs) of inverter are investigated.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.36-42
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• 2007

A low-power compact driver for multistandard physical layer is presented. The proposed driver achieves low power and small area through the voltage-mode driver with trans-impedance configuration and the novel hybrid driver,. In the voltage-mode driver, a trans-impedance configuration alleviates the problem of limited common-mode range of error amplifiers and the area and power overhead due to pre-amplifier. For a standard with extended output swing, only current sources are added in parallel with the voltage-mode driver, which is named a 'hybrid driver'. The hybrid architecture not only increases output swing but reduces overall driver area. The overall driver occupies $0.14mm^2$. Power consumptions under 3.3-V supply are 24.5 mW for the voltage-mode driver and 44.5 mW for the hybrid driver.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.375-378
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• 2013

A reference voltage generator which is insensitive to PVT (process-voltage-temperature) variation necessary for NVM memory IPs such as EEPROM and MTP memories is designed in this paper. The designed BGR (bandgap reference voltage) circuit based on MagnaChip's $0.18{\mu}m$ EEPROM process uses a low-voltage bandgap reference voltage generator of cascode current-mirror type with a wide swing and shows a reference voltage characteristic insensitive to PVT variation. The minimum operating voltage is 1.43V and the VREF sensitivity against VDD variation is 0.064mV/V. Also, the VREF sensitivity against temperature variation is $20.5ppm/^{\circ}C$. The VREF voltage has a mean of 1.181V and its three sigma ($3{\sigma}$) value is 71.7mV.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.4
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• pp.49-58
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• 2014

A low-swing differential near-ground signaling (NGS) transceiver for low-power high-speed mobile I/O interface is presented. The proposed transmitter adopts an on-chip regulated programmable-swing voltage-mode driver and a pre-driver with asymmetric rising/falling time. The proposed receiver utilizes a new multiple gain-path differential amplifier with feed-forward capacitors that boost high-frequency gain. Also, the receiver incorporates a new adaptive bias generator to compensate the input common-mode variation due to the variable output swing of the transmitter and to minimize the current mismatch of the receiver's input stage amplifier. The use of the new simple and effective impedance matching techniques applied in the transmitter and receiver results in good signal integrity and high power efficiency. The proposed transceiver designed in a 65-nm CMOS technology achieves a data rate of 13 Gbps/channel and 0.3 pJ/bit (= 0.3 mW/Gbps) high power efficiency over a 10 cm FR4 printed circuit board.