• 제어로봇시스템학회:학술대회논문집
• /
• 1996.10b
• /
• pp.601-604
• /
• 1996

It is well known that steam generator water level control at low power operation has many difficulties in a PWR (pressurized water reactor) nuclear power plant. The reverse process responses known as shrink and swell effects make it difficult to control the steam generator water level at low power. A new automatic control logic to remove the reverse process responses is proposed in this paper. It is implemented in PLC (programmable logic controller) and evaluated by using test equipment in Korea Atomic Energy Research Institute. The simulation test shows that the performance requirements is met at low power (below 15%). The water level control by new control logic is stabilized within 1% fluctuation from setpoint, while the water level by YGN 3 and 4 control logic is unstable with the periodic fluctuation of 25% magnitude at 5% power.

• 제어로봇시스템학회:학술대회논문집
• /
• 2001.10a
• /
• pp.114.6-114
• /
• 2001

According to expansion of wireless communication system and mobile device, interest has been growing in personal navigation system integrated with wireless system. In portable consumer electronics, such as cellular phones, GPS and PDA, one of major design factors is the power consumption. Solutions of reducing the power dissipation are low voltage, low system clock power management and so on. This paper develops a GPS receiver based on the advanced power management algorithm that achieves very low average power consumption. Both RF and DSP chips are powered down and reactivated only when the position fixing is required. In order to run, the developed includes the RTC calibration function and the fast reacquisition function using XMC (eXtended Multiple Correlator) ...

• ETRI Journal
• /
• v.34 no.5
• /
• pp.727-733
• /
• 2012

This paper demonstrates a new driving scheme that allows reducing the supply voltage of data drivers for low-power active matrix organic light-emitting diode (AMOLED) displays. The proposed technique drives down the data voltage range by 50%, which subsequently diminishes in the peak power consumption of data drivers at the full white pattern by 75%. Because the gate voltage of a driving thin film transistor covers the same range as a conventional driving scheme by means of a level-shifting scheme, the low-data supply scheme achieves the equivalent dynamic range of OLED currents. The average power consumption of data drivers is reduced by 60% over 24 test images, and power consumption is kept below 25%.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2005.05a
• /
• pp.863-866
• /
• 2005

Low-power design is one of the most important challenges encountered in maximizing battery life in portable devices as well as saving energy during system operation. In this paper we propose a low-power DCT (Discrete Cosine Transform) architecture using a modified Computation Sharing Multiplication (CSHM). The overall rate of power consume is reduced during DCT: the proposed architecture does not perform arithmetic operations on unnecessary bits during the Computation Sharing Multiplication calculations. Experimental results show that it is possible to reduce power dissipation up to about $7{\sim}8%$ without compromising the final DCT results. The proposed lowpower DCT architecture can be applied to consumer electronics as well as portable multimedia systems requiring high throughput and low-power.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.501-502
• /
• 2006

In this paper low power high gain amplifier is suitable for application in low power systems was designed and fabricated. The amplifier used both subthreshold bias for low power and positive feedback Q-enhancement technique for high gain. The amplifier used TSCM $0.18{\mu}m$ RF CMOS technology measures a power gain of 32.3dB, a quality factor of 366 and a power consumption of 3mW in a supply voltage of 1.8V.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.10a
• /
• pp.892-895
• /
• 2011

Power consumption during testing System-On-Chip (SOC) are becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.67 no.6
• /
• pp.738-744
• /
• 2018

This paper proposes a low cost hot swap operation circuit of a parallel operation power supply for servers. Hot swap function for server power system is essential in 24 hour operation system such as internet data center, server, factory and etc. Server power supplies used in internet data centers have two or more parallel operations with the hot swap operation. However, the cost of the power supply is high because the controller IC for hot swap operation is very expensive. Therefore, this paper proposes a parallel-operated power supply with a low-cost hot swap controller for servers. The proposed system can operate hot swap function by using discrete devices and reduce the cost by more than 50%. A 1.2kW prototype system is implemented to verify the proposed low cost hot swap controller.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.9 no.4
• /
• pp.240-248
• /
• 2009

Moore's law has driven silicon technology scale down aggressively, and it results in significant increase of leakage current on nano-meter scale CMOS. Especially, in mobile devices, leakage current has been one of designers' main concerns, and thus many studies have introduced low power methodologies. However, there are few studies to minimize implementation cost in the mixed use of the methodologies to the best of our knowledge. In this paper, we introduce industrial applications of low power design methodologies for the decrease of leakage current. We focus on the design cost reduction of power gating and reverse body bias when used together. Also, we present voltage scale as an alternative to reverse body bias. To sustain gate leakage current, we discuss the adoption of high-$\kappa$ metal gate, which cuts gate leakage current by a factor of 10 in 32 nm CMOS technology. A 45 nm mobile SoC is shown as the case study of the mixed use of low power methodologies.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.10 no.5
• /
• pp.587-592
• /
• 2015

According to increase in the use of the LED, the demand for low power consumption LED display design of the controller block has increased. In this paper, the low power LED controller block was designed through the power source supply that leads adiabatic operation from constant current source circuit operated by digital signal control. The proposed circuit was implemented using a 0.35um CMOS process. and it demonstrated linear operation of the circuit. From the simulation result, the proposed circuit was evaluated with about 82% power consumption reduction effect in comparison with conventional LED controller block. This research is expected to be helpful for the low power operation and the solution for heat problem of LED display.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.25 no.6
• /
• pp.9-17
• /
• 2011

The high-power LED (Light Emitting Diode) which is recently gaining popularity as a digital light source has such advantages as low power consumption, long life, fast switching speed, and high efficiency. Thus, many efforts are being made to use the high-power LEDs for general lighting. This paper proposes LED driving circuit uses a DC/DC converter that can recover energy to compensate for the current variations caused by changes in LED equivalent resistance following a temperature change instead of serial resistance. The maximum input voltage of this DC/DC converter has low voltage variations by temperature change when the rated current is formed. In order to return current to the input side, we need a high boosting at low power. Thus, to improve the low efficiency of power converter, the power converter can be configured in such a way to gather the powers of low-capacity DC/DC converters and return the total power. Experiments showed that the proposed system improved efficiency compared to the conventional LED drive using the existing DC/DC converter.