• International Journal of Fluid Machinery and Systems
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• 제6권2호
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• pp.49-55
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• 2013

Water lubricated guide bearing was newly released and has been applied to actual hydro turbines with vertical shaft. As a result, they can have not only high bearing performance but environmental advantages in meeting the demand for reducing river pollution by oil leakage from oil lubricated guide bearing. The PTFE composite guide bearing was tested by experimental equipment operated under conditions similar to those of actual hydro turbines. Circumferential and axial tilting bearing segments help to improve the bearing performance and efficiency due to low friction loss in the bearing system. Furthermore, bearing cooling systems could be eliminated and maintenance periods could be extended, thus the initial investment and operating costs of the hydroelectric power plant are reduced.

• 한국산학기술학회논문지
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• 제13권4호
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• pp.1814-1821
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• 2012

본 논문은 국내에서 설비용량 20MW 이상의 신재생발전기에 대해 계통연계 유지조건을 의무화하는 송배전용 전기설비 이용규정이 2012년부터 적용됨에 따라 이를 모의해석 기반의 풍력발전기 계통연계 검토 시에 고려하기 위한 풍력발전기의 LVRT(Low Voltage Ride Through) 전사모형을 개발하고 이를 풍력발전기가 연계된 전력계통의 성능평가에 적용하여 전사모델의 유용성을 검증한 후 전력계통의 대표적인 상정고장에 적용하여 국내 풍력발전기 계통연계 유지조건의 적용효과를 분석하였다.

• 한국산업정보학회논문지
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• 제18권5호
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• pp.59-65
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• 2013

저전력 설계를 요구하는 디지털 시스템에서는 동적 전력(dynamic power)과 누설 전력(leakage power) 사이의 균형을 이루는 점에 근접하는 매우 낮은 전압에서 작동하는 디지털 설계 방식을 요구하지만, 기존의 동기방식의 회로는 낮은 전압에서 지연(delay)이 급격히 증가하여 시스템의 전체 성능을 유지할 수 없을 뿐만 아니라, 공정, 전압, 온도 변이 (PVT variation) 등에 크게 영향을 받아서 올바른 동작을 기대할 수 없다. 따라서 본 논문에서는 낮은 전압에서 여러 가지 변이들에 영향을 받지 않는 비동기회로 설계 방식 중에 타이밍 분석이 요구되지 않고, 설계가 간단한 NCL (Null Convention Logic) 방식을 사용한 저전력 산술논리 연산장치 (ALU) 회로를 매그나칩-SK하이닉스 0.18um 공정으로 설계하고, 기존의 파이프라인 방식의 ALU와 스피드와 전력에 관해서 비교하였다.

• IEIE Transactions on Smart Processing and Computing
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• 제2권4호
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• pp.248-254
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• 2013

The size and power consumption of digital circuits including the dimming circuit part will increase for high-performance solid state lighting (SSL) systems in the future. This study examined the low-power consumption of adiabatic dynamic CMOS logic (ADCL) due to the principles of adiabatic charging. Furthermore, the designed low-power ADCL digital pulse width modulation (PWM) was optimized for SSL dimming systems. For this purpose, an ADCL digital 3-bit PWM was optimized in two steps. In the first step, the architecture of the ADCL digital 3-bit PWM was miniaturized. In the second step, the clock cut-off circuit was designed and added to the ADCL PWM. As a result, compared to the original configuration, 60 transistors and 15 capacitors of ADCL digital 3-bit PWM were reduced for miniaturization. Moreover, the clock cut-off circuit, which controls wake-up and sleep mode of ADCL D-FFs, was designed. The power consumption of an optimized ADCL digital PWM for all bit patterns decreased by 54 %.

• Journal of Electrical Engineering and Technology
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• 제12권2호
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• pp.726-737
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• 2017

The use of energy storage systems (ESSs) has become a feasible solution to solve the wind power intermittency issue. However, the use of ESSs increases the system cost significantly. In this paper, an optimal power flow control scheme to minimize the ESS capacity is proposed by using the zero-phase delay low-pass filter which can eliminate the phase delay between the dispatch power and the wind power. In addition, the filter time constant is optimized at the beginning of each dispatching interval to ensure the fluctuation mitigation requirement imposed by the grid code with a minimal ESS capacity. And also, a short-term power dispatch control algorithm is developed suitable for the proposed power dispatch based on the zero-phase delay low-pass filter with the predetermined ESS capacity. In order to verify the effectiveness of the proposed power management approach, case studies are carried out by using a 3-MW wind turbine with real wind speed data measured on Jeju Island.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권3호
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• pp.165-175
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• 2010

This paper presents a fine-grain supply-voltage-control scheme for low-power FPGAs. The proposed supply-voltage-control scheme detects the critical path in real time with small overheads by exploiting features of asynchronous architectures. In an FPGA based on the proposed supply-voltage-control scheme, logic blocks on the sub-critical path are autonomously switched to a lower supply voltage to reduce the power consumption without system performance degradation. Moreover, in order to reduce the overheads of level shifters used at the power domain interface, a look-up-table without level shifters is employed. Because of the small overheads of the proposed supply-voltage-control scheme and the power domain interface, the granularity size of the power domain in the proposed FPGA is as fine as a single four-input logic block. The proposed FPGA is fabricated using the e-Shuttle 65 nm CMOS process. Correct operation of the proposed FPGA on the test chip is confirmed.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(1)
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• pp.31-34
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• 2004

In wireless communication systems, low-power metrics is becoming a burdensome problem in the portable terminal design, because of portability constraints. This paper presents design architecture of a low-power partial correlation Digital Matched Filter for the IMT-2000 communication systems. The proposed approach focuses on efficient circuit size, power dissipation, maintaining the operating throughput. The proposed architecture was verified by using Xilinx FPGA.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제4권1호
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• pp.79-83
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• 2004

This paper presents the performance analysis for CPL based design of a Low power digital neuroprocessor. We have verified the functionality of the components at the high level using Verilog and carried out the simulations in Silos. The components of the proposed digital neuroprocessor have also been verified at the layout level in LASI. The layouts have then been simulated and analyzed in Winspice for their timing characteristics. The result shows that the proposed digital neuroprocessor consistently consumes less power than other designs of the same function. It can also be seen that the proposed functions have lesser propagation delay and thus higher speed compared to the other designs.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 C
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• pp.2089-2091
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• 2000

Pulsed power systems consist of a capacitor bank, an isolated high-voltage charging power-supply, high-current bus-work for charging and discharging and a control system. In such pulsed power systems, the operating-lifetime of the capacitors is closely dependent on the voltage reversal. Hence, most capacitor-discharging systems includes crowbar circuits. The crowbar circuit prevents the capacitor recharging with reverse voltage. Usually it consists of crowbar resistors and high pulse-current diode-stacks connected in series. The requirements for the diode-stacks are fast-recovery time and high-voltage and large-current ratings, which results in the high cost of the pulsed-power system. This paper presents a protection scheme of a charging and discharging system of a 500kJ capacitor bank using a low-cost crowbar circuit and safety-fuses.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2015년도 전력전자학술대회 논문집
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• pp.487-488
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• 2015

New inverter motor drive systems consume 30%~50% less energy compared to existing motor drive systems. For inverter motor drive systems, the development of a 1200V high side driver is critical. This paper presents an advanced 1200V high side driver with low power consumption and high ruggedness. This solution implements a high voltage level shifter which consumes low power by adding a clamped VGS LDMOS driver to the conventional short pulse generator. Moreover, this paper proposes a highly rugged 1200V LDMOS which improves SOA by limiting the hole current. This paper could be applied to smart power modules used for HVAC (heating, ventilation, and airconditioning) and industrial inverters. Consequently, this paper will provide design engineers with an understanding of how they can make a significant contribution to worldwide energy savings.