• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.425-428
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• 2017

This paper describes a full-wave rectifiers for energy harvesting circuit using a vibrational energy. The designed circuit is applied to the negative voltage converter with the body-bias technique using the Beta-multiplier so that the power efficiency is excellent even at the low voltage, and the comparator is designed as the bulk-driven type. The proposed circuit is designed with $0.35{\mu}m$ CMOS process, and The designed chip occupies $931{\mu}m{\times}785{\mu}m$.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.4
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• pp.91-96
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• 2001

In this paper we propose a new ENMODL(Enhanced-NORA-MODL) CLA(Carry-Look Ahead Adder) for high speed and low power multiplier. To reduce transistor counts, area and power dissipation we developed new-approaches. The method makes use of a dynamic CMOS logic ENMODL CLA. The advantage of ENMODL is small area and high speed The speed of ENMODL CLA is invreased by 6.27 % as compared with conventional NMOCL CLA. The proposed method was verified by HSPICE simulation and layout througth 0.6${\mu}{\textrm}{m}$ CMOS process.

• Journal of Electrical Engineering and Technology
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• v.12 no.1
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• pp.189-197
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• 2017

This paper elaborates two novel proposed topologies (type-I and type-II) of the high step-up DC-DC converter using switched inductor and voltage multiplier cell. The advantages of these proposed topologies are the less voltage stress on semiconductor devices, low device count, high power conversion efficiency, high switch utilization factor and high diode utilization factor. We analyze the Type-II topologies operating principle and mathematical analysis in detail in continuous conduction mode. High-intensity discharge lamp for the automotive application can use the derived topologies. The proposed converters give better performance when compared to the existing types. Also, it is found that the proposed type-II converter has relatively higher voltage gain compared to the type-I converter. A 40 W, 12 V input voltage and 72 V output voltage has developed for the type-II converter and the performances are validated.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.5
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• pp.1143-1150
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• 2000

A dual-mode multiplier (DMM) that performs single- and double-precision multiplications has been designed using a $0.25-\mum$ 5-metal CMOS technology. An algorithm for efficiently implementing double-precision multiplication with a single-precision multiplier was proposed, which is based on partitioning double-precision multiplication into four single-precision sub-multiplications and computing them with sequential accumulations. When compared with conventional double-precision multipliers, our approach reduces the hardware complexity by about one third resulting in small silicon area and low-power dissipation at the expense of increased latency and throughput cycles. The DMM consists of a $28-b\times28-b$ single-precision multiplier designed using radix-4 Booth receding and redundant binary (RB) arithmetic, an accumulator and a simple control logic for mode selection. It contains about 25,000 transistors on the area of about $0.77\times0.40-m^2$. The HSPICE simulation results show that the DMM core can safely operate with 200-MHZ clock at 2.5-V, and its estimated power dissipation is about 130-㎽ at double-precision mode.

• Proceedings of the KIEE Conference
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• 2003.07c
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• pp.1821-1823
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• 2003

We propose a high voltage dc-dc converter for CW(continuous wave) $CO_2$ laser system using a current resonant half-bridge inverter and a Cockcroft-Walton circuit. This high voltage power supply includes a 2-stage voltage multiplier driven by a regulated half-bridge series resonant inverter. The inverter drives a step-up transformer and the transformer secondary is applied to the voltage multiplier. Thus, it has high efficiency because of the less switching losses by virtue of the current resonant half-bridge inverter, and also compact size, small parasitic capacitance in the transformer stage owing to the low number of a winding turn of the step up transformer secondary by combining with Cockroft-Walton circuit. We could be obtained the maximum laser output power of 44 W and the maximum system efficiency of over 16 %.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.33-38
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• 2009

The group CSD (GCSD) multiplier was recently proposed based on the variation of canonic signed digit (CSD) encoding and partial product sharing. This multiplier provides an efficient design when the multiplications are performed only with a few predetermined coefficients (e.g., FFT). In many DSP applications such as FFT, the (2W-1)-bit product obtained from W-bit multiplicand and W-bit multiplier is quantized to W-bits by eliminating the (W-1) least-significant bits. This paper presents an error compensation method for a fixed-width GCSD multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate for the quantization error, the encoded signals from the GCSD multiplier are used for the generation of error compensation bias. By Synopsys simulations, it is shown that the proposed method leads to up to 84% reduction in power consumption and up to 79% reduction in area compared with the fixed-width modified Booth multiplier.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.9
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• pp.657-662
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• 2004

The low-power design of the digital hearing aid is indispensable to achieve the compact portable device with long battery duration. In this paper, new low-power adaptive filter structure is proposed based on distributed arithmetic(DA). By modifying the DA technique, the proposed decimation filter structure can significantly reduce the power consumption and implementation area. Through Verilog-HDL coding, cell occupation of the proposed structure is reduced to 33.49% in comparison with that of the conventional multiplier structure. Since Verilog-HDL simulation processing time of the two structures are same, it is assumed that the power consumption or implementation area is proportional to the cell occupation in the simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.6C
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• pp.603-613
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• 2006

Low-power design is one of the most important challenges encountered in maximizing battery life in portable devices as well as saving energy during system operation. In this paper we propose a low-power DCT (Discrete Cosine Transform) architecture using a modified Computation Sharing Multiplication (CSHM). The overall rate of Power consumption is reduced during DCT: the proposed architecture does not perform arithmetic operations on unnecessary bits during the Computation Sharing Multiplication calculations. Experimental results show that it is possible to reduce power dissipation up to about $7\sim8%$ without compromising the final DCT results. The proposed low-power DCT architecture can be applied to consumer electronics as well as portable multimedia systems requiring high throughput and low-power.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1280-1283
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• 2002

This paper discusses issues in VLSI design and implementation of high performance datapath circuits. Of particular concern will he various types of multiplier and adder, which are fundamental to DSP operations. Performance comparison will be provided in terms of sampling speed, layout area, and in particular, power consumption, with techniques that may be applied to reduce power dissipation also suggested. As an example, a low power, high performance recursive filter achieved through bit-level pipelining technique is illustrated

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.424-424
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• 2004