• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.2C
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• pp.298-305
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• 2004

This paper presents an error compensation method for a fixed-width modified Booth multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate for the quantization error, Booth encoder outputs (not multiplier coefficients) are used for the generation of error compensation bias. The truncated bits are divided into two groups depending upon their effects on the quantization error. Then, different error compensation methods are applied to each group. By simulations, it is shown that quantization error can be reduced up to 50％ by the proposed error compensation method compared with the existing method with approximately the same hardware overhead in the bias generation circuit. It is also shown that the proposed method leads to up to 40％ reduction in area and power consumption of a multiplier compared with the ideal multiplier.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.739-742
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• 2002

This article proposes a Four-Quadrant Analog Multiplier (4-QAM) applying switched-capacitor and pulse-width amplitude modulation (PWAM) principles. The features of the presented circuit are that it can function as analog multiplier with a wide dynamic range of input signal and no disturbing from deviation of carrier frequency of PWM signal. In addition, the circuit detail is simpler than that of the previously proposed circuits. It is then easy and applicable for employing it into Integrated Circuit (IC) realization to especially operate in low-frequency and low-power applications. The experimental results granted are in correspondence to the theoretical analysis.

• Journal of Electrical Engineering and Technology
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• v.12 no.4
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• pp.1484-1494
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• 2017

We present a two-stage inverter with high step-up conversion ratio engaging modified finite-set Model Predictive Control (MPC) for utility-integrated photovoltaic (PV) applications. The anticipated arrangement is fit for low power PV uses, the calculated efficiency at 150 W input power and 19 times boosting ratio was around 94%. The suggested high-gain dc-dc converter based on Cockcroft-Walton multiplier constitutes the first-stage of the offered structure, due to its high step-up ability. It can boost the input voltage up to 20 times. The 3S current-source inverter constitutes the second-stage. The 3S current-source inverter hires three semiconductor switches, in which one is functioning at high-frequency and the others are operating at fundamental-frequency. The high-switching pulses are varied in the procedure of unidirectional sine-wave to engender a current coordinated with the utility-voltage. The unidirectional current is shaped into alternating current by the synchronized push-pull configuration. The MPC process are intended to control the scheme and achieve the subsequent tasks, take out the Maximum Power (MP) from the PV, step-up the PV voltage, and introduces low current with low Total Harmonic Distortion (THD) and with unity power factor with the grid voltage.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.83-85
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• 2019

The use of high voltage gain converters is essential for the distributed power generation systems with renewable energy sources such as the fuel cells and solar cells due to their low voltage characteristics. In this paper, a high voltage gain topology combining cascode Inverting Buck-Boost converter and voltage multiplier structure is introduced. In proposed converter, the input voltage is connected in series at the output, the portion of input power is directly delivered to the load which results in continuous input current. In addition, the voltage multiplier stage stacked in proper manner is not only enhance high step-up voltage gain ratio but also significantly reduce the voltage stress across all semiconductor devices and capacitors. As a result, the high current-low voltage switches can be employed for higher efficiency and lower cost. In order to show the feasibility of the proposed topology, the operation principle is presented and the steady-state characteristic is analyzed in detail. A 380W-40/380V prototype converter was built to validate the effectiveness of proposed converter.

• KIEE International Transactions on Electrophysics and Applications
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• v.3C no.4
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• pp.123-129
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• 2003

We propose a high voltage dc-dc converter for a CW (continuous wave) $CO_2$ laser system using a current resonant half-bridge inverter and a Cockcroft-Walton circuit. This high voltage power supply includes a 2-stage voltage multiplier driven by a regulated half-bridge series resonant inverter. The inverter drives a step-up transformer and the secondary transformer is applied to the voltage multiplier. It is highly efficient because of the reduced amount of switching losses by virtue of the current resonant half-bridge inverter, and also due to the small size, low parasitic capacitance in the transformer stage owing to the low number of winding turns of the step up secondary transformer combined with the Cockroft-Walton circuit. We obtained a maximum laser output power of 44 W and a maximum system efficiency of over 16%.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.43-49
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• 2000

In this paper, the CMOS four-quadrant analog multipliers for low-voltage low-power applications ate presented. The circuit approach is based on the characteristic of the LV(Low-Voltage) composite transistor which is one of the useful analog building blocks. SPICE simulations are carried out to examine the performances of the designed multipliers. Simulation results are obtained by 0.6${\mu}{\textrm}{m}$ CMOS parameters with 2V power supply. The LV composite transistor can easily be extended to perform a four-quadrant multiplication. The multiplier has a linear input range up to $\pm$0.5V with a linearity error of less than 1%. The measured -3㏈ bandwidth is 290MHz and the power dissipation is 373㎼. The proposed multiplier is expected to be suitable for analog signal processing applications such as portable communication equipment, radio receivers, and hand-held movie cameras.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.9
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• pp.55-65
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• 2000

In this paper, we propose a hardware reduced multiplier for DSP applications. In many DSP applications, all of multiplier products were not used, but only upper bits of product were used. Kidambi proposed truncated unsigned multiplier for this idea. in this paper, we adopt this scheme to Booth multiplier which can be used real DSP systems. Also, zero input guarantees zero output that was not provided in previous paper. In addition, we propose bit extension scheme to reduce truncation error more and more. And, we adopted this multiplier to FIR filters for more efficient design.

• The KIPS Transactions:PartA
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• v.10A no.6
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• pp.671-676
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• 2003

In this paper, we proposed a new First Partial product Addition (FPA) architecture with new compressor (or parallel counter) to CSA tree built in the process of adding partial product for improving speed in the fast parallel multiplier to improve the speed of calculating partial product by about 20% compared with existing parallel counter using full Adder. The new circuit reduces the CLA bit finding final sum by N/2 using the novel FPA architecture. A 5.14nS of multiplication speed of the $16{\times}16$ multiplier is obtained using $0.25\mu\textrm{m}$ CMOS technology. The architecture of the multiplier is easily opted for pipeline design and demonstrates high speed performance.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.49-52
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• 2003

Two types of ozone monitors using UV absorption method were tried in consideration of cost of the monitor and precision in measuring. The high concentration ozone monitor for high concentration real time ozone monitoring from ozone generator was composed of a low pressure mercury lamp as UV source, a photo multiplier tube as UV detector and signal processing unit for the most part. This structure could be very useful for low price high concentration ozone monitor due to simple system structure and fairly good monitoring characteristics. The developed system showed good linear output characteristics to ozone in the measuring concentration range of 0.05 and 2 wt.%. For accuracy ambient ozone monitoring in ambient in ppm level, the system composed of a high power pulsed xenon lamp as UV source, an optical spectrometer with a high sensitivity linear CCD array as UV detector and signal processing unit in brief speaking was proposed our study for the first time in the world. The developed system showed good linearity and sensitivity in relative low measuring range between 10ppm and 10,000ppm, and showed some feasibility of high resolution ozone monitor using CCD array as photodetector.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.852-855
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• 2002

This paper presents a design of FIR near-equiripple Nyquist filters having zero-intersymbol interference (ISI) and low sensitivity to timing jitter, with coefficients taking only discrete values. Using an affine scaling linear programming algorithm, an optimum discrete coefficient set can be obtained in a feasible computational time. Also presented is a pipelined multiplier-free FIR filter realization with periodically time-varying (PTV) coefficients based on a hybrid form suitable for Nyquist filter. The realization exploits the coefficient symmetry to reduce the hardware by about one half. High speed computation and low power consumption are achieved by its pipelined and low fan-out structure.