• Journal of Power Electronics
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• v.17 no.3
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• pp.590-600
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• 2017

This paper presents a ripple-free input current modified interleaved boost converter for high step-up applications. By integrating dual coupled inductors and voltage multiplier techniques, the proposed converter can reach a high step-up gain without an extremely high turn-ON period. In addition, a very small auxiliary inductor employed in series to the input dc source makes the input current ripple theoretically decreased to zero, which simplifies the design of the electromagnetic interference (EMI) filter. In addition, the voltage stresses on the semiconductor devices of the proposed converter are efficiently reduced, which makes high performance MOSFETs with low voltage rated and low resistance $r_{DS}$(ON) available to reduce the cost and conduction loss. The operating principles and steady-state analyses of the proposed converter are introduced in detail. Finally, a prototype circuit rated at 400W with a 42-50V input voltage and a 400V output voltage is built and tested to verify the effectiveness of theoretical analysis. Experimental results show that an efficiency of 95.3% can be achieved.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.11-20
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• 1998

High-speed complex-number arithmetic units are essential to baseband signal processing of modern digital communication systems such as channel equalization, timing recovery, modulation and demodulation. In this paper, a new complex-number multiplication algorithm is proposed, which is based on redundant binary (RB) arithmetic combined with radix-4 Booth recoding scheme. The proposed algorithm reduces the number of partial product by one-half as compared with the conventional direct method using real-number multipliers and adders. It also leads to a highly parallel architecture and simplified circuit, resulting in high-speed operation and low power dissipation. To demonstrate the proposed algorithm, a prototype complex-number multiplier-accumulator (CMAC) core with 10-bit operands has been designed using 0.8-$\mu\textrm{m}$ N-Well CMOS technology. The designed CMAC core contains about 18,000 transistors on the area of about 1.60 ${\times}$ 1.93 $\textrm{mm}^2$. The functional and speed test results show that it can operate with 120-MHz clock at V$\sub$DD/=3.3-V, and its power consumption is given to about 63-mW.

• ETRI Journal
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• v.41 no.5
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• pp.626-636
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• 2019

A novel algorithm for joint user selection and optimal power allocation for Stackelberg game-based revenue maximization in a downlink non-orthogonal multiple access (NOMA) network is proposed in this study. The condition for the existence of optimal solution is derived by assuming perfect channel state information (CSI) at the transmitter. The Lagrange multiplier method is used to convert the revenue maximization problem into a set of quadratic equations that are reduced to a regular chain of expressions. The optimal solution is obtained via a univariate iterative procedure. A simple algorithm for joint optimal user selection and power calculation is presented and exhibits extremely low complexity. Furthermore, an outage analysis is presented to evaluate the performance degradation when perfect CSI is not available. The simulation results indicate that at 5-dB signal-to-noise ratio (SNR), revenue of the base station improves by at least 15.2% for the proposed algorithm when compared to suboptimal schemes. Other performance metrics of NOMA, such as individual user-rates, fairness index, and outage probability, approach near-optimal values at moderate to high SNRs.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.1
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• pp.61-67
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• 2014

Conventional synchronous circuits in low power required systems such as sensor systems cannot only satisfy the timing requirement of the low voltage digital systems, but also they may generate wrong outputs under the influence of PVT variations and aging effects. Therefore, in the reliable ultra-low power design, asynchronous circuits have recently been reconsidered as a solution for scaling issues. However, it is not easy to totally replace synchronous circuits with asynchronous circuits in the digital systems, so the interfacing between the synchronous and asynchronous circuits is indispensable for the digital systems. This paper presents a new design for interfacing between asynchronous circuits and synchronous circuits, and the interface circuits are applied to a $4{\times}4$ multiplier logic designed using 0.11um technology.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.24-30
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• 2003

This study focuses on the arithmetical methodology and hardware implementation of low system-complexity A $B^2$＋C operator over GF(2$^{m}$ ) using the irreducible AOP of degree m. The proposed parallel-in parallel-out operator is composed of CS, PP, and MS modules, each can be established using the array structure of AND and XOR gates. The proposed multiplier is composed of (m＋1)$^2$ 2-input AND gates and (m＋1)(m＋2) 2-input XOR gates. And the minimum propagation delay is $T_{A}$ ＋(1＋$\ulcorner$lo $g_2$$^{m}$ $\lrcorner$) $T_{x}$ . Comparison result of the related A $B^2$＋C operators of GF(2$^{m}$ ) are shown by table, It reveals that our operator involve more lower circuit complexity and shorter propagation delay then the others. Moreover, the interconnections of the out operators is very simple, regular, and therefore well-suited for VLSI implementation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.3
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• pp.462-469
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• 2001

In this paper, local oscillator in K band using low frequency noise upconversion gain anaylsis was designed and measured. We extended Two Signal Method(TSM) to estimate upconversion gain and resulting phase noise. To confirm the validity of the proposed method, a free-running oscillator which had low upconversion gain was designed. The measured oscillation frequency was 23.42 GHz and phase noise at 1 MHz of offset was -105.2 dBc/Hz. Also, this oscillator was operated for subharmonic injection locked osci1lator(SILO). In this case, SILO showed ideal frequency multiplier phase noise characteristics at low subharmonic injection power level.

• Journal of Energy Engineering
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• v.25 no.2
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• pp.94-100
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• 2016

ESS(Energy Storage System) is an important source that keeps power supply stable and utilizes electricity efficiently. For example, ESS contributes to resolve power supply imbalance, stabilize new renewable energy output and regulate frequency. ESS is predicted to be expanded to 55.9GWh of installed capacity by 2023, which is 30 times more than that of 2014. To raise competitiveness of domestic ESS industry in this increasing world market, we have disseminated load-shift ESS for continuous power supply imbalance with FR ESS, and also necessity to secure domestic track record is required. However in case of FR ESS, utility of installing thermal power plant is generally generated within 5% range of rated capacity, so that scalability of domestic market is low without dramatic increase of thermal power plant. Necessity of load-shift ESS dissemination is also decreasing effected by surplus backup power securement policy, raising demand for new dissemination model. New dissemination model is promising for $CO_2$ reduction effect in spite of intermittent output. By stabilizing new renewable energy output in connection with new renewable energy, and regulating system input timing of new renewable energy generation rate, it is prospected model for 'post-2020' regime and energy industry. This research presents a policy alternatives of REC multiplier calculation method to induce investment after outlining PV-connected ESS charge/discharge mode to reduce GHG emission, This alternative is projected to utilize GHG emission reduction methodology for 'Post-2020' regime, big issue of new energy policy.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.2
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• pp.112-118
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• 2015

Conventional synchronous circuits cannot keep the circuit performance, and cannot even guarantee correct operations under the influence of PVT variations and aging effects in the nanometer regime. Therefore, in this paper, a DI (delay insensitive) design based NCL (Null Convention Logic) design methodology with a very simple design structure has been used to design digital systems, which is one of well-known asynchronous design methods robust to various variations and does not require any timing analysis. Because circuit-level structures of conventional NCL gates have weakness of low speed, high area overhead or high wire complexity, this paper proposes a new lNCL gates designed at the transistor level for high-speed, low area overhead, and low wire complexity. The proposed NCL gate libraries have been compared to the conventional NCL gates in terms of circuit delay, area and power consumption using a asynchronous multiplier implemented in dongbu 0.11um CMOS technology.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.3
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• pp.270-276
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• 2018

This paper presents a low area 256-point pipelined FFT architecture, especially for IEEE 802.16a WiMAX systems. Radix-24 algorithm and single-path delay feedback (SDF) architecture are adopted in the design to reduce the complexity of twiddle factor multiplication. A new cascade canonical signed digit (CSD) complex multipliers are proposed for twiddle factor multiplication, which has lower area and less power consumption than conventional complex multipliers composed of 4 multipliers and 2 adders. Also, the proposed cascade CSD multipliers can remove look-up table for storing coefficient of twiddle factors. In hardware implementation with Cyclone 10LP FPGA, it is shown that the proposed FFT design method achieves about 62% reduction in gate count and 64% memory reduction compared with the previous schemes.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.105-108
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• 2001

4 32-bit RISC core is designed for embedded application and DSP. This processor offers low power consumption by fully static operation and compact code size by efficient instruction set. Processor performance is improved by wing conditional instruction execution, block data transfer instruction, multiplication instruction, bunked register file structure. To support compact code size of embedded application, It is capable cf executing both 16-bit instructions and 32-bit instruction through mixed mode instruction conversion Furthermore, for fast MAC operation for DSP applications, the processor has a dedicated hardware multiplier, which can complete a 32-bit by 32-bit integer multiplication within seven clock cycles. These result in high instruction throughput and real-time interrupt response. This chip is implemented with 0.35${\mu}{\textrm}{m}$, 4- metal CMOS technology and consists of about 50K gate equivalents.