• Journal of IKEEE
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• v.11 no.2
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• pp.83-88
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• 2007

This paper proposes an 8${\times}$8 bit parallel multiplier using MOS current-mode logic (MCML) circuit for low power consumption. The 8${\times}$8 multiplier is designed with proposed MCML full adders and conventional full adders. The designed multiplier is achieved to reduce the power consumption by 9.4% and the power-delay-product by 11.7% compared with the conventional circuit. This circuit is designed with Samsung 0.35${\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of Power System Engineering
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• v.18 no.5
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• pp.129-136
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• 2014

This paper proposes improvement on sensorless vector control performance of a permanent magnet synchronous motor (PMSM) with sliding mode observer. An adaptive observer gain and second order cascade low-pass filter (LPF) were used to improve the estimation accuracy of the rotor position and speed. The adaptive observer gain was applied to suppress the chattering intensity and obtained by using the Lyapunov's stability criterion. The second order cascade LPF was designed for the system to escalate the filtering performance of the back-emf estimation. Furthermore, genetic algorithm was used to optimize the system PI controller's performance. Simulation results showed the effectiveness of the suggested improvement strategy. Moreover, the strategy was useful for the sensorless vector control of PMSM to operate on the low-speed area.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.433-434
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• 2007

This paper describes a low-voltage dynamic random-access memory (DRAM) focusing on subthreshold leakage reduction during self-refresh (sleep) mode. By sharing a power switch, multiple iterative circuits such as row and column decoders have a significantly reduced subthreshold leakage current. To reduce the leakage current of complex logic gates, dual channel length scheme and input vector control method are used. Because all node voltages during the standby mode are deterministic, zigzag super-cutoff CMOS is used, allowing to Preserve internal data. MTCMOS technique Is also used in the circuits having no need to preserve internal data. Sub-1.2-V 1-Gb mobile DDR DRAM employing all these low-power techniques was designed in a 60 nm CMOS technology and achieved over 77% reduction of overall leakage current during the self-refresh mode.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.1
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• pp.91-98
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• 1999

An integrated ZCS quasi-resonant converter(QRC) for the power factor correction with a single switch is presented in this paper. The power factor correction can be achieved by the discontinuous conduction mode(DCM) operation of the input current. The proposed converter gives the good power factor, low line current harmonics, and tight output regulation. The input current waveform of the prototype designed using design equations shows about 15% of total harmonic distortion at rated condition. Also, the efficiency and power factor can be obtained about 86% and 0.985, respectively, at rated condition. The proposed converter is suitable for a low power level converter with a tightly regulated low output voltage and switching frequency of more than several hundreds kHz.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1609-1618
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• 2015

DC microgrids are considered as prospective systems because of their easy connection of distributed energy resources (DERs) and electric vehicles (EVs), reduction of conversion loss between dc output sources and loads, lack of reactive power issues, etc. These features make them very suitable for future industrial and commercial buildings' power systems. In addition, the bipolar-type dc system structure is more popular, because it provides two voltage levels for different power converters and loads. To keep voltage balanced in such a dc system, a bidirectional dual buck-boost voltage balancer with direct coupling is introduced based on P-cell and N-cell concepts. This results in greatly enhanced system reliability thanks to no shoot-through problems and lower switching losses with the help of power MOSFETs. In order to increase system efficiency and reliability, a novel burst-mode control strategy is proposed for the dual buck-boost voltage balancer. The basic operating principle, the current relations, and a small-signal model of the voltage balancer are analyzed under the burst-mode control scheme in detail. Finally, simulation experiments are performed and a laboratory unit with a 5kW unbalanced ability is constructed to verify the viability of the bidirectional dual buck-boost voltage balancer under the proposed burst-mode control scheme in low-voltage bipolar-type dc microgrids.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.802-809
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• 2014

This paper presents a dual-mode bias modulator (BM) for complementary metal oxide semiconductor (CMOS) power amplifiers (PAs). The BM includes a hybrid buck converter and a normal buck converter for an envelope tracking (ET) mode for high output power and for an average power tracking (APT) mode for low output power, respectively. The dual-mode BM and CMOS PA are designed using a $0.18-{\mu}m$ CMOS process for the 1.75 GHz band. For the 16-QAM LTE signal with a peak-to-average power ratio of 7.3 dB and a bandwidth of 5 MHz, the PA with the ET mode exhibited a poweradded efficiency (PAE) of 39.2%, an EVM of 4.8%, a gain of 19.0 dB, and an adjacent channel leakage power ratio of -30 dBc at an average output power of 22 dBm, while the stand-alone PA has a PAE of 8% lower at the same condition. The PA with APT mode has a PAE of 21.3%, which is an improvement of 13.4% from that of the stand-alone PA at an output power of 13 dBm.

• International Journal of Aeronautical and Space Sciences
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• v.17 no.4
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• pp.631-640
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• 2016

A dual-mode power management for a hybrid-electric UAV with a cruise power of 200W is proposed and empirically verified. The subject vehicle is a low-speed long-endurance UAV powered by a solar cell, a fuel cell, and a battery pack, which operate in the same voltage bounds. These power sources of different operational characteristics can be managed in two different methods: passive management and active management. This study proposes a new power management system named PMS2, which employs a bypass circuit to control the individual power sources. The PMS2 normally operates in active mode, and the bypass circuit converts the system into passive mode when necessary. The output characteristics of the hybrid system with the PMS2 are investigated under simulated failures in the power sources and the conversion of the power management methods. The investigation also provides quantitative comparisons of efficiencies of the system under the two distinct power management modes. In the case of the solar cell, the efficiency difference between the active and the passive management is shown to be 0.34% when the SOC of the battery is between 25-65%. However, if the SOC is out of this given range, i.e. when the SOC is at 90%, using active management displays an improved efficiency of 6.9%. In the case of the fuel cell, the efficiency of 55% is shown for both active and passive managements, indicating negligible differences.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1813-1820
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• 2016

Dual-mode photovoltaic power system should be capable of operating in grid-connected (GC) and stand-alone (SA) modes for distributed generation. Under different working modes, the optimal parameters of inverter output filters vary. Inverters commonly operate in GC mode, and thus, a small capacitance is beneficial to the GC topology for achieving a reasonable compromise. A predictive current control scheme is proposed to control the grid current in GC mode and thereby obtain high-performance power. As filter are not optimal under SA mode, a compound control strategy consisting of predictive current control, instantaneous voltage control, and repetitive control is proposed to achieve low total harmonic distortion and improve the output voltage spectrum. The seamless transfer between GC mode and SA mode is illustrated in detail. Finally, the simulation and experimental results of a 4 kVA prototype demonstrate the effectiveness of the proposed control strategy.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.4
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• pp.49-58
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• 2014

A low-swing differential near-ground signaling (NGS) transceiver for low-power high-speed mobile I/O interface is presented. The proposed transmitter adopts an on-chip regulated programmable-swing voltage-mode driver and a pre-driver with asymmetric rising/falling time. The proposed receiver utilizes a new multiple gain-path differential amplifier with feed-forward capacitors that boost high-frequency gain. Also, the receiver incorporates a new adaptive bias generator to compensate the input common-mode variation due to the variable output swing of the transmitter and to minimize the current mismatch of the receiver's input stage amplifier. The use of the new simple and effective impedance matching techniques applied in the transmitter and receiver results in good signal integrity and high power efficiency. The proposed transceiver designed in a 65-nm CMOS technology achieves a data rate of 13 Gbps/channel and 0.3 pJ/bit (= 0.3 mW/Gbps) high power efficiency over a 10 cm FR4 printed circuit board.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.3
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• pp.207-214
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• 2019

In this study, discrete-time domain analysis is proposed to investigate the input current of a buck AC/DC light-emitting diode (LED) driver. The buck power factor correction converter can operate in both discontinuous conduction mode (DCM) and continuous conduction mode (CCM). Two discontinuous and two continuous conduction operating modes are possible depending on which event terminates the conduction of the main switch in a switching cycle. All four operating modes are considered in the discrete-time domain analysis. The peak current-mode control with slope compensation is used to design a low-cost AC/DC LED driver. A slope compensation design of the buck AC/DC LED driver is described on the basis of a discrete-time domain analysis. Experimental results are presented to confirm the usefulness of the proposed analysis.