• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.339-340
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• 2006

In this paper, a low-power deblocking filter structure for H.264 video coding algorithm is proposed. By sharing addition hardware for common filter coefficients, we have designed an efficient deblocking filter structure. Proposed deblocking filter utilizes MUX and DEMUX circuits for input data sharing and shows 44.2% reduction for add operation. In the HDL coding simulation and FPGA implementation, we achieved 19.5% and 19.4% gate count reduction, respectively, comparison with the conventional deblocking filter structure.

• 한국산업정보학회논문지
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• 제21권4호
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• pp.21-30
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• 2016

In a single-phase power factor correction (PFC), the standard cascaded control algorithm using a proportional-integral-derivative (PID) controller has two main drawbacks: an inability to track sinusoidal current reference and low harmonic compensation capability. These drawbacks cause poor power factor and high harmonics in grid current. To improve these drawbacks, this paper uses a proportional-integral-derivative-resonant (PIDR) controller which combines a type-III PID with proportional-resonant (PR) controllers in the PFC. Based on a small signal model of the PFC, the type-III PID controller was implemented taking into account the bandwidth and phase margin of the PFC system. To adopt the PR controllers, the spectrum of inductor current of the PFC was analyzed in frequency domain. The hybrid PIDR controller were simulated using PSCAD/EMTDC and implemented on a 3 kW PFC prototype hardware. The performance results of the hybrid PIDR controller were compared with those of an individual type-III PID controller. Both controllers were implemented successfully in the single-phase PFC. The total harmonic distortion of the proposed controller were much better than those of the individual type-III PID controller.

• Journal of Electrical Engineering and Technology
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• 제11권6호
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• pp.1656-1663
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• 2016

A capacitive wireless power transfer (C-WPT) system uses an electric field to transmit power through a physical isolation barrier which forms a pair of ac link capacitors between the metal plates. However, the physical dimension and low dielectric constant of the interface medium severely limit the effective link capacitance to a level comparable to the main switch output capacitance of the transmitting circuit, which thus narrows the soft-switching range in the light load condition. Moreover, by fundamental limit analysis, it can be proved that such a low link capacitance increases operating frequency and capacitor voltage stress in the full load condition. In order to handle these problems, this paper investigates optimal design of double matching transformer networks for C-WPT. Using mathematical analysis with fundamental harmonic approximation, a design guideline is presented to avoid unnecessarily high frequency operation, to suppress the voltage stress on the link capacitors, and to achieve wide ZVS range even with low link capacitance. Simulation and hardware implementation are performed on a 5-W prototype system equipped with a 256-pF link capacitance and a 200-pF switch output capacitance. Results show that the proposed scheme ensures zero-voltage-switching from full load to 10% load, and the switching frequency and the link capacitor voltage stress are kept below 250 kHz and 452 V, respectively, in the full load condition.

• 한국정보통신학회논문지
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• 제15권9호
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• pp.1993-1999
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• 2011

한국기술표준원(KATS)과 국제표준화기구(ISO/IEC)에 의해 표준으로 채택된 블록암호 알고리듬 HIGHT용 저면적/저전력 암호/복호 코어를 설계하였다. HIGHT 알고리듬은 USN, RFID와 같은 유비쿼터스 환경에 적합하도록 개발되었으며, 128 비트 마스터 키를 사용하여 64 비트 평문을 64 비트 암호문으로, 또는 그 역으로 변환한다. 저면적과 저전력 구현을 위해 암호화 및 복호화를 위한 라운드 변환 블록과 키 스케줄러의 하드웨어 자원이 공유되도록 설계를 최적화하였다. 0.35-${\mu}m$ CMOS 표준 셀 라이브러리를 이용한 합성결과, HIGHT64 코어는 3,226 게이트로 구현되었으며, 80-MHz@2.5-V로 동작하여 150-Mbps의 성능을 갖는 것으로 평가되었다.

• Journal of Power Electronics
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• 제10권4호
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• pp.365-373
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• 2010

This paper proposes a hybrid single carrier sinusoidal modulation suitable for multiphase multilevel inverters. Multiphase multilevel inverters are controlled by hybrid modulation to provide multiphase variable voltage and a variable frequency supply. The proposed modulation combines the benefits of fundamental frequency modulation and single carrier sinusoidal modulation (SC-SPWM) strategies. The main characteristics of hybrid modulation are a reduction in switching losses and improved harmonic performance. The proposed algorithm can be applied to cascaded multilevel inverter topologies. It has low computational complexity and it is suitable for hardware implementations. SC-SPWM and its base modulation design are implemented on a TMS320F2407 digital signal processor (DSP). A Complex Programmable Logic Device realizes the hybrid PWM algorithm and it is integrated with a DSP processor for hybrid SC-SPWM generation. The feasibility of this hybrid modulation is verified by spectral analysis, power loss analysis, simulation and experimental results.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2014년도 추계학술대회
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• pp.285-287
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• 2014

한국기술표준원(KATS)과 국제표준화기구(ISO/IEC)에 의해 표준으로 채택된 경량 블록암호 알고리듬 HIGHT용 저면적/저전력 암호/복호 코어를 설계하였다. IoT(Internet of Things) 보안에 적합하도록 개발된 경량 블록암호 알고리듬 HIGHT는 128비트의 마스터 키를 사용하여 64비트의 평문을 64비트의 암호문으로, 또는 그 역으로 변환한다. 저면적과 저전력 구현을 위해 data path를 32 비트로 축소하여 설계하였으며, 암호화 및 복호화를 위한 라운드 변환 블록과 키 스케줄러의 하드웨어 자원이 공유되도록 설계를 최적화하였다.

• ETRI Journal
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• 제30권2호
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• pp.315-325
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• 2008

In this paper, we first investigate the side channel analysis attack resistance of various FPGA hardware implementations of the ARIA block cipher. The analysis is performed on an FPGA test board dedicated to side channel attacks. Our results show that an unprotected implementation of ARIA allows one to recover the secret key with a low number of power or electromagnetic measurements. We also present a masking countermeasure and analyze its second-order side channel resistance by using various suitable preprocessing functions. Our experimental results clearly confirm that second-order differential side channel analysis attacks also remain a practical threat for masked hardware implementations of ARIA.

• ETRI Journal
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• 제32권1호
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• pp.1-10
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• 2010

In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency-division multiplexing ultra-wideband systems. The proposed 128-point FFT processor employs both a modified radix-$2^4$ algorithm and a radix-$2^3$ algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure-sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 ${\mu}m$ CMOS technology with a supply voltage of 1.8 V. The hardware- efficient 128-point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128-point mixed-radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128-point FFT architectures.

• 한국통신학회논문지
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• 제35권2B호
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• pp.215-224
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• 2010

컨테이너 보안장치(CSD)는 컨테이너의 도어를 통한 침입을 감시하는 장치이며, IEEE 802.15.4의 비컨 모드에서 RFD로 동작한다. 그러나 비컨 모드에서는 CSD 리더가 없어도 주기적으로 리더의 신호를 탐지하게 되므로 배터리 소모가 크다. CSD는 목적지에 도착할 때까지 이상없이 동작해야 하므로 배터리 소모를 줄이고, 위험 발생 시 CSD 리더에게 능동적으로 메시지를 전달해야 한다. 본 논문에서는 미국 DHS의 CSD 규격에 부합하는 저전력 CSD를 제안한다. 제안하는 CSD는 전력 소모를 최소화한 하드웨어 디자인과 저전력 동작기법인 불침번 기법, 저전력 센싱 기능을 통해 배터리 소모를 줄인다. 또한 위험 상황 발생 시 리더에게 능동적으로 경고 메시지를 전달한다. 성능 평가 결과 제안한 CSD는 불침번 기법을 통해 배터리 소모를 70% 이상 줄이고, 저전력 센싱 기능을 통해 불필요한 센싱을 80% 이상 감소시키며, 직접적인 통신 거리 밖에 있는 리더에게 94%가 넘는 확률로 메시지를 전달할 수 있음을 보였다.

• 전자공학회논문지C
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• 제34C권9호
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• pp.22-32
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• 1997

This paper proposes an imprecise compuitation model for DCT considering QOS of images and a two dimensional DCT architecture for imprecise computations. In case that many processes are scheduling in a hard real time system, the system resources are shared among them. Thus all processes can not be allocated enough system resources (such as processing power and communication bandwidth). The imprecise computtion model can be used to provide scheduling flexibility and various QOS(quality of service)levels, to enhance fault tolerance, and to ensure service continuity in rela time systems. The DCT(discrete cosine transform) is known as one of popular image data compression techniques and adopted in JPEG and MPEG algorithms since the DCT can remove the spatial redundancy of 2-D image data efficiently. Even though many commercial data compression VLSI chips include the DCST hardware, the DCT computation is still a very time-consuming process and a lot of hardware resources are required for the DCT implementation. In this paper the DCT procedure is re-analyzed to fit to imprecise computation model. The test image is simulated on teh base of this model, and the computation time and the quality of restored image are studied. The row-column algorithm is used ot fit the proposed imprecise computation DCT which supports pipeline operatiions by pixel unit, various QOS levels and low speed stroage devices. The architecture has reduced I/O bandwidth which could make its implementation feasible in VLSI. The architecture is proved using a VHDL simulator in architecture level.