• Title/Summary/Keyword: low-noise electronics

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A 170㎼ Low Noise Amplifier Using Current Reuse Gm-boosting Technique for MedRadio Applications (전류 재사용 Gm-boosting 기술을 이용한 MedRadio 대역에서의 170㎼ 저잡음 증폭기)

  • Kim, InSoo;Kwon, Kuduck
    • Journal of the Institute of Electronics and Information Engineers
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    • v.54 no.2
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    • pp.53-57
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    • 2017
  • This paper proposes a 401MHz-406MHz low noise amplifier for MedRadio applications. The proposed low noise amplifier adopts a common gate amplifier topology using current reuse gm-boosting technique. The proposed low noise amplifier shows better performance of voltage gain and noise figure than the conventional gm-boosted common gate amplifier in the same power consumption. The proposed current-reuse gm-boosted low noise amplifier achieves a voltage gain of 22 dB, a noise figure of 2.95 dB, and IIP3 of -17 dBm while consuming $170{\mu}W$ from a 0.5 V supply voltage in $0.13{\mu}m$ CMOS process.

An Effective Noise Estimator for Use in Noise Reduction

  • Han, Hag-Yong;Kwon, Ho-Min;Lee, Sung-Mok;Lee, Gi-Dong;Kang, Bong-Soon
    • Journal of information and communication convergence engineering
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    • v.9 no.1
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    • pp.59-63
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    • 2011
  • Conventional noise reduction filtering schemes realize limited improvements of the peak signal-to-noise ratio (PSNR) in the low-level noisy images. The flatness degree and the edge information are effectively used to estimate the noise volume. We propose a noise estimator for reducing noise in the AWGN (additive white gaussian noise) corrupted images using three intermediate image maps (FGM(flatness gray map), FIM(flatness index map), NEM(noise estimate map)). The proposed noise estimator is fed into the conventional noise reduction filters as a pre-processor. The performance of noise reduction is tested in the various AWGN corrupted images.

A 5.5 GHz VCO with Low-Frequency Noise Suppression (저주파 잡음이 억압된 5.5 GHz 전압제어발진기)

  • Lee J.Y;Bae B.C.;Lee S.H.;Kang J.Y;Kim B.W.;Oh S.H
    • Proceedings of the IEEK Conference
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    • 2004.06b
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    • pp.465-468
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    • 2004
  • In this paper, we describe the design and implementation of the new current-current negative feedback (CCNF) voltage-controlled oscillator (VCO), which suppresses 1/f induced low-frequency noise. By means of the CCNF, the high-frequency noise as well as the low-frequency noise is prevented from being converted into phase noise. The proposed CCNF VCO shows 11-dB reduction in phase noise at 10 kHz offset, compared with the conventional differential VCO. The phase noise of the proposed VCO is -87 dBc/Hz at 10 kHz offset frequency from 5.5-GHz carrier. The proposed VCO consumes 14.0 mA at 2.0 V supply voltage, and shows single-ended output power of -12.0 dBm.

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A Low-Noise High Performance Amplifier for Low Input Signals (저입력신호를 위한 저잡음 고성능 증폭기)

  • 이대영
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.9 no.4
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    • pp.17-24
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    • 1972
  • A simply constructed and inexpensive amplifier that exhibits unusually low noise is studied. The high-performance differential amplifier combines high input impedence, adjustable gain, low in put noise and low output impedance. The amplifier is particularly useful in applications which call for large amplificaions of very low level signals.

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A MedRadio-Band Low Power Low Noise Amplifier for Medical Devices (의료기기용 MedRadio 대역 저전력 저잡음 증폭기)

  • Kim, Taejong;Kwon, Kuduck
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.9
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    • pp.62-66
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    • 2016
  • This paper presents a MedRadio-band low power low noise amplifier for Medical Devices. A proposed MedRadio-band low power low noise amplifier adopts a current-reuse resistive feedback topology to increase overall gm and reduce power consumption. The gain of the LNA increases by the Q-factor of the additional series RLC input matching network, and its noise figure is minimized by the similar factor. Furthermore, it consumes low power because of low supply voltage and current reuse technique. By exploiting the $g_m$-booting and matching network property, the proposed MedRadio-band low noise amplifier achieves a noise figure of 0.85 dB, a voltage gain of 30 dB, and IIP3 of -7.9 dBm while consuming 0.18 mA from a 1 V supply voltage in $0.13{\mu}m$ CMOS technology.

High-Gain Wideband CMOS Low Noise Amplifier with Two-Stage Cascode and Simplified Chebyshev Filter

  • Kim, Sung-Soo;Lee, Young-Sop;Yun, Tae-Yeoul
    • ETRI Journal
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    • v.29 no.5
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    • pp.670-672
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    • 2007
  • An ultra-wideband low-noise amplifier is proposed with operation up to 8.2 GHz. The amplifier is fabricated with a 0.18-${\mu}m$ CMOS process and adopts a two-stage cascode architecture and a simplified Chebyshev filter for high gain, wide band, input-impedance matching, and low noise. The gain of 19.2 dB and minimum noise figure of 3.3 dB are measured over 3.4 to 8.2 GHz while consuming 17.3 mW of power. The Proposed UWB LNA achieves a measured power-gain bandwidth product of 399.4 GHz.

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An Ultra Wideband Low Noise Amplifier in 0.18 μm RF CMOS Technology

  • Jung Ji-Hak;Yun Tae-Yeoul;Choi Jae-Hoon
    • Journal of electromagnetic engineering and science
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    • v.5 no.3
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    • pp.112-116
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    • 2005
  • This paper presents a broadband two-stage low noise amplifier(LNA) operating from 3 to 10 GHz, designed with 0.18 ${\mu}m$ RF CMOS technology, The cascode feedback topology and broadband matching technique are used to achieve broadband performance and input/output matching characteristics. The proposed UWB LNA results in the low noise figure(NF) of 3.4 dB, input/output return loss($S_{11}/S_{22}$) of lower than -10 dB, and power gain of 14.5 dB with gain flatness of $\pm$1 -dB within the required bandwidth. The input-referred third-order intercept point($IIP_3$) and the input-referred 1-dB compression point($P_{ldB}$) are -7 dBm and -17 dBm, respectively.

Low Noise and Low Power IC Using Opamp Sharing Technique for Capacitive Micro-Sensor Sensing Platform (증폭기 공유 기법을 이용한 저전력 저잡음 용량형 센서용 신호 처리 IC)

  • Park, Yunjong;Kim, Choul-Young;Jung, Bang Chul;Yoo, Hoyoung;Ko, Hyoungho
    • Journal of Sensor Science and Technology
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    • v.26 no.1
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    • pp.60-65
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    • 2017
  • This paper describes the low noise and low power IC using the opamp sharing technique for the capacitive micro-sensor sensing platform. The proposed IC reduces noise using correlated double sampling (CDS) and reduces power consumption using the opamp sharing technique. The IC is designed to be fully programmable, and can be digitally controlled by serial peripheral interface (SPI). The power consumption and the integrated input referred noise are 1.02 mW from a 3.3 V supply voltage and $0.164aF_{RMS}$ with a bandwidth of 400 Hz. The capacitive sensitivity, the input-output linearity and the figure of merits (FoM) are 2.5 mV/fF, 2.46 %FSO, and 8.4, respectively.

CMI Tolerant Readout IC for Two-Electrode ECG Recording (공통-모드 간섭 (CMI)에 강인한 2-전극 기반 심전도 계측 회로)

  • Sanggyun Kang;Kyeongsik Nam;Hyoungho Ko
    • Journal of Sensor Science and Technology
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    • v.32 no.6
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    • pp.432-440
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    • 2023
  • This study introduces an efficient readout circuit designed for two-electrode electrocardiogram (ECG) recording, characterized by its low-noise and low-power consumption attributes. Unlike its three-electrode counterpart, the two-electrode ECG is susceptible to common-mode interference (CMI), causing signal distortion. To counter this, the proposed circuit integrates a common-mode charge pump (CMCP) with a window comparator, allowing for a CMI tolerance of up to 20 VPP. The CMCP design prevents the activation of electrostatic discharge (ESD) diodes and becomes operational only when CMI surpasses the predetermined range set by the window comparator. This ensures power efficiency and minimizes intermodulation distortion (IMD) arising from switching noise. To maintain ECG signal accuracy, the circuit employs a chopper-stabilized instrumentation amplifier (IA) for low-noise attributes, and to achieve high input impedance, it incorporates a floating high-pass filter (HPF) and a current-feedback instrumentation amplifier (CFIA). This comprehensive design integrates various components, including a QRS peak detector and serial peripheral interface (SPI), into a single 0.18-㎛ CMOS chip occupying 0.54 mm2. Experimental evaluations showed a 0.59 µVRMS noise level within a 1-100 Hz bandwidth and a power draw of 23.83 µW at 1.8 V.

A Low Noise and Low Power RF Front-End for 5.8-GHz DSRC Receiver in 0.13 ㎛ CMOS

  • Choi, Jae-Yi;Seo, Shin-Hyouk;Moon, Hyun-Won;Nam, Il-Ku
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.11 no.1
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    • pp.59-64
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    • 2011
  • A low noise and low power RF front-end for 5.8 GHz DSRC (Dedicated Short Range Communication) receiver is presented. The RF front-end is composed of a single-to-differential two-stage LNA and a Gilbert down-conversion mixer. In order to remove an external balun and 5.8 GHz LC load tuning circuit, a single-to-differential LNA with capacitive cross coupled pair is proposed. The RF front-end is fabricated in a 0.13 ${\mu}m$ CMOS process and draws 7.3 mA from a 1.2 V supply voltage. It shows a voltage gain of 40 dB and a noise figure (NF) lower than 4.5 dB over the entire DSRC band.