References
-
S. Shin, et al, "
$0.18{\mu}m$ CMOS integrated chipset for 5.8 GHz systems with +10 dBm output power," in Proc. IEEE Int. Symp. Circuits and Systems, May, 2008, pp.1958-1961. https://doi.org/10.1109/ISCAS.2008.4541828 - T. Masuda, et al, "Single-chip 5.8 GHz ETC transceiver IC with PLL and demodulation circuits using SiGe HBT/CMOS," in IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb., 2002, pp. 96-97. https://doi.org/10.1109/ISSCC.2002.992956
- M. Nagata, et al, “5.8 GHz RF transceiver LSI including on-chip matching circuits,” in Proc. IEEE Bipolar Circuits and Technology Meeting, Maastrict, Netherland, pp.263-266, Oct., 2006.
- S. Shinjo, et al, "ASK and Pi/4-QPSK dual mode SiGe-MMIC transceiver for 5.8 GHz DSRC terminals having stabilized amplifier chain," in IEEE MTT-S Dig., Jun., 2008, pp.1071-1074. https://doi.org/10.1109/MWSYM.2008.4633021
- N. Sasho, et al, "Single-chip 5.8 GHz DSRC transceiver with dual-mode of ASK and pi/4-QPSK," in IEEE Radio and Wireless Symp., Jan., 2008, PP.799-802. https://doi.org/10.1109/RWS.2008.4463613
- S.-H. Lee, et al, “A 5.8 GHz MMIC down-conversion mixer for DSRC receiver using SiGe BiCMOS process,” in Proc. Asia-Pacific Conf. Comm., 5-5 Oct., 2008, pp.586-589.
- K. Kwon, et al, “A 5.8 GHz integrated CMOS dedicated short Range communication transceiver for the Korea/Japan electronic toll collection System”, IEEE Trans. Microw. Theory Tech., Vol. 58, No.11, pp.2751-2763, Nov., 2010. https://doi.org/10.1109/TMTT.2010.2077891
- I. Nam, et al, “CMOS RF amplifier and mixer circuits utilizing complementary characteristics of parallel combined NMOS and PMOS devices,” IEEE Trans. Microw. Theory Tech., Vol.53, No.5, pp.1662-1671, May, 2005. https://doi.org/10.1109/TMTT.2005.847059
- Signal converter having compensation circuit and method thereof, Korea Patent 0916542, Sep., 2009.
- S.-S. Choi, et al, “A 2.4/5.2-GHz dual band CMOS VCO using balanced frequency doubler with gate bias matching network”, Journal of Semiconductor Technology and Science, Vol.9, No.4, pp.192-197, Dec., 2009. https://doi.org/10.5573/JSTS.2009.9.4.192
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