• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.2
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• pp.319-324
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• 2014

The wafer carrier is made of PP, PC, PE resin which have excellent heat and chemical resistance and electrical properties. However, particle generation has become a problem due to static electricity generated in the carrier. Some conductive material such as carbon black (CB) and carbon fiber (CF) are added for the purpose of anti-static, however, additional for motility and particle contamination problems due to high carbon content occurs. In this paper, the electrical characteristics and workability are observed and compared by adding low Carbon Nono Tube(CNT) to each PP, PC and PE resin to solve the problem.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.12
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• pp.871-876
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• 2014

Efficiency of crystalline Si solar cell can be maximized as minimizing optical loss through antireflection texturing with inverted pyramids. Even if cost-competitive, soft lithography can be employed instead of photolithography for the purpose, some limitations still remain to apply the soft lithography directly to as-received solar grade wafer with a bunch of micro trenches on surface. Therefore, it is needed to develop a low-cost, effective planarization process and evaluate its output to be applicable to patterning process with PDMS stamp. In this study new surface planarization process is proposed and the change of micro scale trenches on the surface as a function of etching time is observed. Also, the effect of trenches on pattern quality by soft lithography is investigated using FEM structural analysis. In conclusion it is clear that the geometry and shape of trenches would be basic considerations for soft lithography application to low quality wafer.

• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1297-1299
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• 1998

LB layers of L-$\alpha$-DLPC deposited by LB method were deposited onto n-type silicon wafer as Z-type film. Films made up of 8, 16 layers of lipid with long alkyl chain and the thickness of monolayer and multilayers was determined by ellipsometry. It was deposited Ag and Al onto LB layers and silicon wafer for electrode and small electrode exhibit high capacitance and low leakage current. The C-V curves of the MLS capacitor shows very high saturation value of capacitance. And cross-sectional SEM image of MLS capacitor indicated the presence of pore with Al electrode and we found that the Ag is good for electrode metal.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.19 no.12
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• pp.1347-1355
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• 2009

This paper demonstrates the validity of spectral element analysis for modeling the high-frequency dynamic behaviors of a beam with a surface-bonded piezoelectric wafer through a laboratory test. In the spectral element analysis, the high-frequency electro-mechanical interaction can be considered properly with relatively low computational cost compared to the finite element analysis. In the verification test, a cantilever beam with a surface-bonded piezoelectric wafer is forced to be in steady-state motion by exerting the harmonic driving voltage signal on the piezoelectric wafer. A laser scanning vibrometer is used to obtain the overall dynamic responses of the structure such as resonance frequencies, the associated mode shapes, and frequency response functions up to 20 kHz. Then, these dynamic responses from the test are compared to those computed by the spectral element analysis. A two-dimensional finite analysis is conducted to obtain the asymptotic solutions for the comparison purpose as well.

• Journal of the Korean institute of surface engineering
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• v.32 no.3
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• pp.239-243
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• 1999

At Present, 200mm wafer technology is being applied for commercial fabrications of 64, 128, and 256 M DRAM devices, and 300mm technology will be evolved for 1G DRAM devices in the early 21th century, recognizing limitations of several process technologies. In particular recognition has been realized in harmful effects of surface contamination of trace metals introduced during devicing processes. Such a guide line for surface metal contamination has been proposed as 1E9 and 1E10 atoms/$\textrm{cm}^2$ of individual metal contamination for wafering and devicing of 1G DRAM, respectively, and so its measurement limit should be at least 1E8 atoms/$\textrm{cm}^2$. The detection limit of present measurement systems is 2E9 atoms/$\textrm{cm}^2$ obtainable with TRXFA(Total Reflection X-Ray Fluorescence Analysis). TRXFA is nondestructive and the simplest in terms of operation, and it maps the whole wafer surfaces but needs detection improvement. X-Ray intensity produced with synchrotron accelerator is much higher than that of conventional X-ray sources by order of 4-5 magnitudes. Hence theoretically its reactivity with silicon surfaces is expected to be much higher than the conventional one, realizing improvement of detection limit. X-ray produced with synchrotron accelerator is illuminated at a very low angle with silicon wafer surfaces such as 0.1 degree and reflects totally. Hence informations only from surface can be collected and utilized without overlapping with bulk informations. This study shows the total reflection phenomenon and quantitative improvement of detection limit for metallic contamination. It is confirmed that synchrotron X-ray can be a very promising alternative for realizing improvement of detection limit for the next generation devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.198-198
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• 2010

The low-k SiOCH thin films were prepared by CCP-PECVD method using BTMSM(Bis-trimethylsilylmethane) precursors deposited on p-Si wafer. The structural complexity originate the complex refractive constants of the films, and resulted the elliptical polarization of the incident linearly polarized light source of Xe-ramp in the range from 190nm to 2100nm. Phase difference and amplitude ratio between s wave and p wave propagating through SiOCH thin film was studied. After annealing, the amplitude of p wave was reduced more than s wave, and phase difference between p and s wave was also reduced.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.21 no.6
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• pp.225-229
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• 2011

Most of the silicon cutting methods using the multi-wire with the slurry injection have been used for wafers of the crystalline solar cell. But the productivity of slurry injection cutting type falls due to low cutting speeds. Also, the direct contact with the metal wire and silicon block increases the concentration of metallic impurities in the wafer's surface. In addition, the abrasive silicon carbide (SiC) generates pollutants. And production costs are rising because it does not re-use the worn wire. On the other hand, the productivity of the cutting method using the diamond coated wire is about 2 times faster than the slurry injection cutting type. Also, the continuous cutting using the used wire of low wear is possible. And this is a big advantage for reduced production costs. Therefore, the cutting method of the diamond coated wire is more efficient than the slurry injection cutting technique. In this study, each cutting type is analyzed using the surface characteristics of the solar wafer and will describe the effects of the manufacturing process of the solar cell. Finally, we will suggest improvement methods of the solar cell process for using the diamond cutting type wafer.

• KIEE International Transactions on Electrophysics and Applications
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• v.2C no.6
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• pp.281-286
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• 2002

The temperature accelerated dielectric breakdown strength of on-wafer low-k dielectric polymer films with thicknesses ranging from 94 nm to 1141 nm is investigated by using the current-voltage characteristic measurements with MIS structures. The temperature dependence of dielectric strength is demonstrated to be Arrhenious for all thicknesses. However, the activation energy is found to be strongly thickness dependent. It follows an exponential relationship rather than being a single value, i.e., the activation energy increase significantly as film thickness increases for the thickness below 500 nm, but it is almost constant for the thickness above 500 nm. This relationship suggests that the change of the activation energy corresponding to different film thickness is closely related to the temperature dependence of the electron trapping/detrapping process in polymer thin films, and is determined by both the trapping rate and the detrapping rate. Thinner films need less energy to form a conduction path compared to thicker films. Hence, it leads to smaller activation energy in thinner films, and the activation energy increases with the increase in film thickness. However, a nearly constant value of the activation energy is achieved above a certain range of film thickness, indicating that the trapping rate and detrapping rate is almost equal and eventually the activation energy approaches the value of bulk material.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.3
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• pp.1-6
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• 2016

The Internet of Things (IoT) is a new technology paradigm demanding one packaged system of various semiconductor and MEMS devices. Therefore, the development of electronic packaging technology with very high connectivity is essential for successful IoT applications. This paper discusses both fan-out wafer level packaging (FOWLP) and 3D stacking technologies to achieve the integrattion of heterogeneous devices for IoT. FOWLP has great advantages of high I/O density, high integration, and design flexibility, but ultra-fine pitch redistribution layer (RDL) and molding processes still remain as main challenges to resolve. 3D stacking is an emerging technology solving conventional packaging limits such as size, performance, cost, and scalability. Among various 3D stacking sequences wafer level via after bonding method will provide the highest connectivity with low cost. In addition substrates with ultra-thin thickness, ultra-fine pitch line/space, and low cost are required to improve system performance. The key substrate technologies are embedded trace, passive, and active substrates or ultra-thin coreless substrates.

• Journal of the Semiconductor & Display Technology
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• v.10 no.4
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• pp.21-23
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• 2011

Uniformity of plasma etching processes critically depends on the wafer temperature and its distribution. The wafer temperature is affected by plasma, chucking force, He back side pressure and the surface temperature of ESC(electrostatic chuck). In this work, 3D mathematical modeling is used to investigate the influence of the geometry of coolant path and the temperature distribution of the ESC surface. The model that has the coolant path with less change of the cross-sectional area and the curvature shows low standard deviation of the ESC surface temperature distribution than the model with the coolant path of the larger surface area and more geometric change.