• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.379-380
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• 2008

This paper presents a wafer-level package using a Dry Film Resist(DFR) for RF MEMS devices. Vertical interconnection is made through the hole formed on the glass cap. Bonding using the DFR has not only less effects on the surface roughness but also low process temperature. We used DFR as adhesive polymer and made the vertical interconnection through Au electroplating. Therefore, we developed a wafer-level package that is able to be used in RF MEMS devices and vertical interconnection.

• Journal of Sensor Science and Technology
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• v.15 no.1
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• pp.58-64
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• 2006

In this study, we describe a low-temperature wafer-level thermocompression bonding using electroplated gold seal line and bonding pads by electroplating method for RF-MEMS devices. Silicon wafers, electroplated with gold (Au), were completely bonded at $320^{\circ}C$ for 30 min at a pressure of 2.5 MPa. The through-hole interconnection between the packaged devices and external terminal did not need metal filling process and was made by gold films deposited on the sidewall of the throughhole. This process was low-cost and short in duration. Helium leak rate, which is measured to evaluate the reliability of bonded wafers, was $2.7{\pm}0.614{\times}10^{-10}Pam^{3}/s$. The insertion loss of the CPW packaged was $-0.069{\sim}-0.085\;dB$. The difference of the insertion loss between the unpackaged and packaged CPW was less than -0.03. These values show very good RF characteristics of the packaging. Therefore, gold thermocompression bonding can be applied to high quality hermetic wafer level packaging of RF-MEMS devices.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.14 no.6
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• pp.104-110
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• 2015

LED has added value as a lighting source in the illuminating industry because of its high efficiency and low power consumption. In LED production processes, the chip cutting process, which mainly uses a scribing process with a laser has an effect on quality and productivity of LED. This scribing process causes problems like heat deformation, decreasing strength. The inner laser method, which makes a void in wafer and induces self-cracking, can overcome these problems. In this paper, cutting sapphire wafer for fabricating LED chip using the inner laser scribing process is proposed and evaluated. The aim is to settle basic experiment conditions, determine parameters of cutting, and analyze the characteristics of cutting by means of experimentation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.5
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• pp.353-360
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• 2012

As semiconductor device technology continuously shrinks, low-open area etch process prevails in front-end etch process, such as contact etch as well as one cylindrical storage (OCS) etch. To eliminate over loaded wafer processing test, it is commonly performed to emply diced small coupons at stage of initiative process development. In nominal etch condition, etch responses of whole wafer test and coupon test may be regarded to provide similar results; however, optical emission spectroscopy (OES) which is frequently utilize to monitor etch chemistry inside the chamber cannot be regarded as the same, especially etch mask is not the same material with wafer chuck. In this experiment, we compared OES data acquired from two cases of etch experiments; one with coupon etch tests mounted on photoresist coated wafer and the other with coupons only on the chuck. We observed different behaviors of OES data from the two sets of experiment, and the analytical results showed that careful investigation should be taken place in OES study, especially in coupon size etch.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.15 no.1
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• pp.34-38
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• 2005

Effects of pH level and slurry particle size on material removal rate and planarization of langasite single crystal wafer have been examined. Higher material removal rate was obtained with lower pH level slurries while the planarization was found to be determined by average particle size of colloidal silica slurries. Slurries containing 0.045 ㎛ amorphous silica particles showed the best polishing effect without any scratches on the surface. Effective particle number has a strong effect on the surface planarization and the removal rate, so that the lower effective particle numbers produced low removal rate but the better planarization results.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1648-1650
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• 1996

In present paper, Cu films $4{\mu}m$, thick were fabricated by dual deposition methods using RF magnetron sputtering on Si wafer. The dependence of the electrical resistivity, adherence, and reflection in Cu films [$Cu_{4-x}$(low resistivity) / $Cu_x$(high adherence) / Si- wafer] on the x thickness have been investigated. Cu films of $4{\mu}m$ thickness formed with dual deposition methods had the low electrical resistivity of about $2.6{\mu}{\Omega}{\cdot}cm$ and high adherence of about 700g/cm. In conclusion, it is possible for these films to be used for micro-devices.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.433-433
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• 2012

As the requirement in patterning geometry continuously shrinks down, the termination of etch process at the exact time became crucial for the success in nano patterning technology. By virtue of real-time optical emission spectroscopy (OES), etch end point detection (EPD) technique continuously develops; however, it also faced with difficulty in low open ratio etching, typically in self aligned contact (SAC) and one cylinder contact (OCS), because of very small amount of optical emission from by-product gas species in the bulk plasma glow discharge. In developing etching process, one may observe that coupon test is being performed. It consumes costs and time for preparing the patterned sample wafers every test in priority, so the coupon wafer test instead of the whole patterned wafer is beneficial for testing and developing etch process condition. We also can observe that etch open area is varied with the number of coupons on a dummy wafer. However, this can be a misleading in OES study. If the coupon wafer test are monitored using OES, we can conjecture the endpoint by experienced method, but considering by data, the materials for residual area by being etched open area are needed to consider. In this research, we compare and analysis the OES data for coupon wafer test results for monitoring about the conditions that the areas except the patterns on the coupon wafers for real-time process monitoring. In this research, we compared two cases, first one is etching the coupon wafers attached on the carrier wafer that is covered by the photoresist, and other case is etching the coupon wafers on the chuck. For comparing the emission intensity, we chose the four chemical species (SiF2, N2, CO, CN), and for comparing the etched profile, measured by scanning electron microscope (SEM). In addition, we adopted the Dynamic Time Warping (DTW) algorithm for analyzing the chose OES data patterns, and analysis the covariance and coefficient for statistical method. After the result, coupon wafers are over-etched for without carrier wafer groups, while with carrier wafer groups are under-etched. And the CN emission intensity has significant difference compare with OES raw data. Based on these results, it necessary to reasonable analysis of the OES data to adopt the pre-data processing and algorithms, and the result will influence the reliability for relation of coupon wafer test and whole wafer test.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.482-485
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• 2004

We fabricated a hybrid bulk/fully depleted silicon on insulator (FDSOI) complementary metal oxide semiconductor (CMOS) active pixel image sensor. The active pixel is comprised of reset and source follower transistors on the SOI seed wafer, while the pinned photodiode and readout gate and floating diffusion are fabricated on the SOI handle wafer after the removal of the buried oxide. The source of dark current is eliminated by hybrid bulk/FDSOI pixel structure between localized oxidation of silicon (LOCOS) and photodiode(PD). By using the low noise hybrid pixel structure, dark currents qm be suppressed significantly. The pinned photodiode can also be optimized for quantum efficiency and reduce the noise of dark current. The spectral response of the pinned photodiode on the SOI handle wafer is very flat between 400 nm and 700 nm and the dark current that is higher than desired is about 10 nA/cm2 at a $V_{DD}$ of 2 V.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.8
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• pp.23-29
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• 2014

We have studied on ozonate water cleaning mechanisms to apply in manufacturing process of 156 mm silicon wafer which is used in the solar cell fabrication. We have analyzed contamination sources on wafer surface which causes poor quality and performance of products in fabrication process, and examined cleaning process using ozonate water to eliminate it. Contamination sources consist of remaining material like organic matter in slurry and detergent and particles in sawing wire. Using this novel technology it is possible for the solar cell wafer to clean with low cost, high performance, and eco-friendly.

• Journal of Powder Materials
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• v.23 no.1
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• pp.43-48
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• 2016

Waste SiC powders obtained from silicon wafer sludge have very low density and a narrow particle size distribution of $10-20{\mu}m$. A scarce yield of C and Si is expected when SiC powders are incorporated into the Fe melt without briquetting. Here, the briquetting variables of the SiC powders are studied as a function of the sintering temperature, pressure, and type and contents of the binders to improve the yield. It is experimentally confirmed that Si and C from the sintered briquette can be incorporated effectively into the Fe melt when the waste SiC powders milled for 30 min with 20 wt.% Fe binder are sintered at $1100^{\circ}C$ upon compaction using a pressure of 250 MPa. XRF-WDS analysis shows that an yield of about 90% is obtained when the SiC briquette is kept in the Fe melt at $1650^{\circ}C$ for more than 1 h.