• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.1
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• pp.329-332
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• 2012

LEDs are using widely in a field of illumination, LCD LED backlight, mobile signals because they have several merits, such as low power consumption, long lifetime, high brightness, fast response, environment friendly. To achieve high performance LEDs, one needs to enhance output power, reduce operation voltage, and improve device reliability. In this paper, we have proposed that the optimum design and specialized process could improve the performance of LED chip. It was showed an output power of 7cd and input supplied voltage of 3.2V by the insertion technique of current blocking layer. In this paper, GaN-based LED chip which is built on the sapphire epi-wafer by selective MOCVD were designed and developed. After that, their performances were measured. It showed the output power of 7cd more than conventional GaN-based chip. It will be used the lighting source of a medical equipment and LCD LED TV with GaN-based LED chip.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.11
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• pp.575-580
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• 2001

In this paper, using $500\mum-thickness\; (100)\; silicon\; wafer,\; flat\; 65\mum-thickness$ silicon mirror plates were fabricated through dry etching and wet etching, and $45\mum-depth$ grooved driving electrodes were fabricated through UV-LIGA process. Four shapes of the driving electrode were fabricated: twenty four grooves of the $50\mum-width$, twelve grooves of the $100\mum-width$, six grooves of the $200\mum-width$, and no grooves on the driving electrode. Fabricated mirror plate size and spring size are $2400\times2400\times65\mum3\; and \;500\times10\times65\mum3,$ respectively. Mirror plate parts and driving electrodes were assembled into the scanning mirrors. Measured natural resonance frequencies were about 600Hz which have error within $\pm 2%$ to calculated value. Due to the squeeze effect in the narrow gap between the mirror plate and the driving electrode, measured resonance frequencies were reduced as raising the amplitude of the mirror plate. In a case of driving electrode without grooves, the resonance frequency was reduced largely, compared with a case of driving electrode with grooves. According to the experimental results, squeeze effect was smaller in the driving electrode with smaller-width and many grooves. Therefore, the driving electrode with smaller-width and many grooves was effective in low voltage and high speed operation.

• Korean Journal of Materials Research
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• v.23 no.10
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• pp.580-585
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• 2013

To observe the formation of defects at the interface between an oxide semiconductor and $SiO_2$, ZnO was prepared on $SiO_2$ with various oxygen gas flow rates by RF magnetron sputtering deposition. The crystallinity of ZnO depends on the characteristic of the surface of the substrate. The crystallinity of ZnO on a Si wafer increased due to the activation of ionic interactions after an annealing process, whereas that of ZnO on $SiO_2$ changed due to the various types of defects which had formed as a result of the deposition conditions and the annealing process. To observe the chemical shift to understand of defect deformations at the interface between the ZnO and $SiO_2$, the O 1s electron spectra were convoluted into three sub-peaks by a Gaussian fitting. The O 1s electron spectra consisted of three peaks as metal oxygen (at 530.5 eV), $O^{2-}$ ions in an oxygen-deficient region (at 531.66 eV) and OH bonding (at 532.5 eV). In view of the crystallinity from the peak (103) in the XRD pattern, the metal oxygen increased with a decrease in the crystallinity. However, the low FWHM (full width at half maximum) at the (103) plane caused by the high crystallinity depended on the increment of the oxygen vacancies at 531.66 eV due to the generation of $O^{2-}$ ions in the oxygen-deficient region formed by thermal activation energy.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.4
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• pp.83-89
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• 2015

In this paper, we propose a fabrication technique for enhanced electrical properties of piezoelectric thick films with excellent patterning property using sol-infiltration and a direct-patterning process. To achieve the needs of high-density and direct-patterning at a low sintering temperature (< $850^{\circ}C$), a photosensitive lead zirconate titanate (PZT) solution was infiltrated into a screen-printed thick film. The direct-patterned PZT films were clearly formed on a locally screen-printed thick film, using a photomask and UV light. Because UV light is scattered in the screen-printed thick film of a porous powder-based structure, there are needs to optimize the photosensitive PZT sol infiltration process for obtaining the enhanced properties of PZT thick film. By optimizing the concentration of the photosensitive PZT sol, UV irradiation time, and solvent developing time, the hybrid films prepared with 0.35 M of PZT sol, 4 min of UV irradiation and 15 sec solvent developing time, showed a very dense with a large grain size at a low sintering temperature of $800^{\circ}C$. It also illustrated enhanced electrical properties (remnant polarization, $P_r$, and coercive field, $E_c$). The $P_r$ value was over four times higher than those of the screen-printed films. These films integrated on silicon wafer substrate could give a potential of applications in micro-sensors and -actuators.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.264-264
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• 2010

Single-walled carbon nanotubes (SWCNTs) were grown on a Si wafer by using thermal chemical vapor deposition (t-CVD). We investigated the effect of the catalyst deposition rate on the types of CNTs grown on the substrate. In general, smaller islands of catalyst occur by agglomeration of a catalyst layer upon annealing as the catalyst layer becomes thinner, which results in the growth of CNTs with smaller diameters. For the same thickness of catalyst, a slower deposition rate will cause a more uniformly thin catalyst layer, which will be agglomerated during annealing, producing smaller catalyst islands. Thus, we can expect that the smaller-diameter CNTs will grow on the catalyst deposited with a lower rate even for the same thickness of catalyst. The 0.5-nm-thick Fe served as a catalyst, underneath which Al was coated as a catalyst support as well as a diffusion barrier on the Si substrate. The catalyst layers were. coated by using thermal evaporation. The deposition rates of the Al and Fe layers varied to be 90, 180 sec/nm and 70, 140 sec/nm, respectively. We prepared the four different combinations of the deposition rates of the AI and Fe layers. CNTs were synthesized for 10 min by flowing 60 sccm of Ar and 60 sccm of $H_2$ as a carrier gas and 20 sccm of $C_2H_2$ as a feedstock at 95 torr and $810^{\circ}C$. The substrates were subject to annealing for 20 sec for every case to form small catalyst islands prior to CNT growth. As-grown CNTs were characterized by using field emission scanning electron microscopy, high resolution transmission electron microscopy, Raman spectroscopy, UV-Vis NIR spectroscopy, and atomic force microscopy. The fast deposition of both the Al and Fe layers gave rise to the growth of thin multiwalled CNTs with the height of ${\sim}680\;{\mu}m$ for 10 min while the slow deposition caused the growth of ${\sim}800\;{\mu}m$ high SWCNTs. Several radial breathing mode (RBM) peaks in the Raman spectra were observed at the Raman shifts of $113.3{\sim}281.3\;cm^{-1}$, implying the presence of SWCNTs (or double-walled CNTs) with the tube diameters 2.07~0.83 nm. The Raman spectra of the as-grown SWCNTs showed very low G/D peak intensity ratios, indicating their low defect concentrations.

• Clean Technology
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• v.16 no.3
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• pp.191-197
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• 2010

Repair reaction of plasma damaged porous methyl doped SiOCH films was carried out with silylation agents dissolved in supercritical carbon dioxide ($scCO_2$) at various reaction time, pressure, and temperature. While a decrease in the characteristic bands at $3150{\sim}3560cm^{-1}$ was detectable, the difference of methyl peaks was not identified apparently in the FT-IR spectra. The surface hydrophobicity was rapidly recovered by the silylation. In order to induce effective repair in bulk phase, the wafer was heat treated before reaction under vacuum or ambient condition. The contact angle was slightly increased after the treatment and completely recovered after the subsequent silylation. Methyl groups were decreased after the plasma damage, but their recovery was not identified apparently from the FT-IR, spectroscopic ellipsometry, and secondary ion mass spectroscopy analyses. Furthermore, Ti evaporator was performed in a vacuum chamber to evaluate the pore sealing effect. The GDS analysis revealed that the open pores in the plasma damaged films were efficiently sealed with the silylation in $scCO_2$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.418-418
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• 2008

The electrochemical etching of silicon in HF-based solutions is known to form various types of porous structures. Porous structures are generally classified into three categories according to pore sizes: micropore (below 2 nm in size), mesopore (2 ~ 50 nm), and macropore (above 50 nm). Recently, the formation of macropores has attracted increasing interest because of their promising characteristics for an wide scope of applications such as microelectromechanical systems (MEMS), chemical sensors, biotechnology, photonic crystals, and photovoltaic application. One of the promising applications of macropores is in the field of MEMS. Anisotropic etching is essential step for fabrication of MEMS. Conventional wet etching has advantages such as low processing cost and high throughput, but it is unsuitable to fabricate high-aspect-ratio structures with vertical sidewalls due to its inherent etching characteristics along certain crystal orientations. Reactive ion dry etching is another technique of anisotropic etching. This has excellent ability to fabricate high-aspect-ratio structures with vertical sidewalls and high accuracy. However, its high processing cost is one of the bottlenecks for widely successful commercialization of MEMS. In contrast, by using electrochemical etching method together with pre-patterning by lithographic step, regular macropore arrays with very high-aspect-ratio up to 250 can be obtained. The formed macropores have very smooth surface and side, unlike deep reactive ion etching where surfaces are damaged and wavy. Especially, to make vertical microwire or nanowire arrays (aspect ratio = over 1:100) on silicon wafer with top-down photolithography, it is very difficult to fabricate them with conventional dry etching. The electrochemical etching is the most proper candidate to do it. The pillar structures are demonstrated for n-type silicon and the formation mechanism is well explained, while such a experimental results are few for p-type silicon. In this report, In order to understand the roles played by the kinds of etching solution and mask patterns in the formation of microwire arrays, we have undertaken a systematic study of the solvent effects in mixtures of HF, dimethyl sulfoxide (DMSO), iso-propanol, and mixtures of HF with water on the structure formation on monocrystalline p-type silicon with a resistivity with 10 ~ 20 $\Omega{\cdot}cm$. The different morphological results are presented according to mask patterns and etching solutions.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.4
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• pp.1-7
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• 1999

We developed Fabrication process of embedded passive components in MCM-D substrate. The proposed MCM-D substrate is based on Cu/photosensitive BCB multilayer. The substrate used is Si wafer and Ti/cu metallization is used to form the interconnect layer. Interconnect layers are formed with 1000$\AA$ Ti/3000$\AA$ Cu by sputtering method and 3$\mu\textrm{m}$ Cu by electrical plating method. In order to form the vias in photosensitive BCB layer, the process of BCB and plasma etch using $C_2F_6$ gas were evaluated. The MCM-D substrate is composed of 5 dielectric layers and 4 interconnect layers. Embedded resistors are made with NiCr and implemented on the $2^{nd}$ dielectric layer. The sheet resistance of NiCr is controlled to be about 21 $\Omega$/sq at the thickness of 600$\AA$. The multi-turn sprial inductors are designed in coplanar fashion on the $4^{th}$ interconnect layer with an underpass from the center to outside using the lower $3^{rd}$ interconnect layer. Capacitors are designed and realized between $1^{st}$ interconnect layer and $2^{nd}$ interconnect layer. An important issue in capacitor is the accurate determination of the dielectric thickness. We use the 900$\AA$ thickness of PECVD silicon nitride film as dielectric. Capacitance per unit area is about 88nF/$\textrm {cm}^2$at the thickness of 900$\AA$. The advantage of this integration process is the compatibility with the conventional semiconductor process due to low temperature PECVD silicon nitride process and thermal evaporation NiCr process.

• Korean Journal of Materials Research
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• v.10 no.12
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• pp.812-818
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• 2000

We studied the effects of Ge preamorphization (PAM) on 0.25$\mu\textrm{m}$ Ti-salicide junctions using comparative study with As PAM. For each PAM schemes, ion implantations are performed at a dose of 2E14 ion/$\textrm{cm}^2$ and at 20keV energy using $^{75}$ /As+and GeF4 ion sources. Ge PAM showed better sheet resistance and within- wafer uniformity than those of As PAM at 0.257m line width of n +/p-well junctions. This attributes to enhanced C54-silicidation reaction and strong (040) preferred orientation of the C54-silicide due to minimized As presence at n+ junctions. At p+ junctions, comparable performance was obtained in Rs reduction at fine lines from both As and Ge PAM schemes. Junction leakage current (JLC) revels are below ~1E-14 A/$\mu\textrm{m}^{2}$ at area patterns for all process conditions, whereas no degradation in JLC is shown under Ge PAM condition even at edge- intensive patterns. Smooth $TiSi_2$ interface is observed by cross- section TEM (X- TEM), which supports minimized silicide agglomeration due to Ge PAM and low level of JLC. Both junction break- down voltage (JBV) and contact resistances are satisfactory at all process conditions.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.200-200
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• 2010

In recent times, metal oxide semiconductors thin films transistor (TFT), such as zinc and indium based oxide TFTs, have attracted considerable attention because of their several advantageous electrical and optical properties. There are many deposition methods for fabrication of ZnO-based materials such as chemical vapor deposition, RF/DC sputtering and pulsed laser deposition. However, these vacuum process require expensive equipment and result in high manufacturing costs. Also, the methods is difficult to fabricate various multicomponent oxide semiconductor. Recently, several groups report solution processed metal oxide TFTs for low cost and non vacuum process. In this study, we have newly developed solution-processed TFTs based on Ti-related multi-component transparent oxide, i. e., InTiO as the active layer. We propose new multicomponent oxide, Titanium indium oxide(TiInO), to fabricate the high performance TFT through the sol-gel method. We investigated the influence of relative compositions of Ti on the electrical properties. Indium nitrate hydrate [$In(NO^3).xH_2O$] and Titanium isobutoxide [$C_{16}H_{36}O_4Ti$] were dissolved in acetylacetone. Then monoethanolamine (MEA) and acetic acid ($CH_3COOH$) were added to the solution. The molar concentration of indium was kept as 0.1 mol concentration and the amount of Ti was varied according to weighting percent (0, 5, 10%). The complex solutions become clear and homogeneous after stirring for 24 hours. Heavily boron (p+) doped Si wafer with 100nm thermally grown $SiO_2$ serve as the gate and gate dielectric of the TFT, respectively. TiInO thin films were deposited using the sol-gel solution by the spin-coating method. After coating, the films annealed in a tube furnace at $500^{\circ}C$ for 1hour under oxygen ambient. The 5% Ti-doped InO TFT had a field-effect mobility $1.15cm^2/V{\cdot}S$, a threshold voltage of 4.73 V, an on/off current ratio grater than $10^7$, and a subthreshold slop of 0.49 V/dec. The 10% Ti-doped InO TFT had a field-effect mobility $1.03\;cm^2/V{\cdot}S$, a threshold voltage of 1.87 V, an on/off current ration grater than $10^7$, and a subthreshold slop of 0.67 V/dec.