• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.3
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• pp.270-276
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• 2018

This paper presents a low area 256-point pipelined FFT architecture, especially for IEEE 802.16a WiMAX systems. Radix-24 algorithm and single-path delay feedback (SDF) architecture are adopted in the design to reduce the complexity of twiddle factor multiplication. A new cascade canonical signed digit (CSD) complex multipliers are proposed for twiddle factor multiplication, which has lower area and less power consumption than conventional complex multipliers composed of 4 multipliers and 2 adders. Also, the proposed cascade CSD multipliers can remove look-up table for storing coefficient of twiddle factors. In hardware implementation with Cyclone 10LP FPGA, it is shown that the proposed FFT design method achieves about 62% reduction in gate count and 64% memory reduction compared with the previous schemes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.2C
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• pp.123-129
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• 2006

In this paper, we concentrate on reducing the complexity for efficient encoder. We design structural LDPC code using circulant matrix and permutation matrix and eIRA code. It is possible to design low complex encoder by using shift register and differential encoder and interleaver than general LDPC encoder that use matrix multiplication operation. The code designed by this structure shows similar performance as random code. And the proposed codes can considerably reduce a number of XOR gates.

• Korean Journal of Computational Design and Engineering
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• v.7 no.2
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• pp.121-130
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• 2002

The concept of Level Of Detail (LOD) was introduced and has been used to enhance display performance and to carry out certain engineering analysis effectively. We would like to use an adequate complexity level for each geometric model depending on specific engineering needs and purposes. Solid modeling systems are widely used in industry, and are applied to advanced applications such as virtual assembly. In addition, as the demand to share these engineering tasks through networks is emerging, the problem of building a solid model of an appropriate resolution to a given application becomes a matter of great necessity. However, current researches are mostly focused on triangular mesh models and various operators to reduce the number of triangles. So we are working on the multi-resolution of the solid model itself, rather than that of the triangular mesh model. In this paper, we propose multi-resolution representation of B-rep model by reordering and converting design features into an enclosing volume and subtractive features.

• International Journal of High-Rise Buildings
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• v.1 no.3
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• pp.203-209
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• 2012

The purpose of this paper is to present the state of practice being used in the Philippines for the performance-based seismic design of reinforced concrete tall buildings. Initially, the overall methodology follows "An Alternative Procedure for Seismic Analysis and Design of Tall Buildings Located in the Los Angeles Region, 2008", which was developed by Los Angeles Tall Buildings Structural Design Council. After 2010, the design procedure follows "Tall Buildings Initiative, Guidelines for Performance-Based Seismic Design of Tall Buildings, 2010" developed by Pacific Earthquake Engineering Research Center (PEER). After the completion of preliminary design in accordance with code-based design procedures, the performance of the building is checked for serviceable behaviour for frequent earthquakes (50% probability of exceedance in 30 years, i.e,, with 43-year return period) and very low probability of collapse under extremely rare earthquakes (2% of probability of exceedance in 50 years, i.e., 2475-year return period). In the analysis, finite element models with various complexity and refinements are used in different types of analyses using, linear-static, multi-mode pushover, and nonlinear-dynamic analyses, as appropriate. Site-specific seismic input ground motions are used to check the level of performance under the potential hazard, which is likely to be experienced. Sample project conducted using performance-based seismic design procedures is also briefly presented.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.300-311
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• 2016

The analog-to-digital-converter-based (ADC-based) backplane receivers that consist of a front-end ADC followed by a digital equalizer are gaining more popularity in recent years, as they support more sophisticated equalization required for high data rates, scale better with fabrication technology, and are more immune to PVT variations. Unfortunately, designing an ADC-based receiver that meets tight power and performance budgets of high-speed backplane link systems is non-trivial as both front-end ADC and digital equalizer can be power consuming and complex when running at high speed. This paper reviews the state of art designs for the front-end ADC and digital equalizers to suggest implementation choices that can achieve high speed while maintaining low power consumption and complexity. Design-space exploration using system-level models of the ADC-based receiver allows through analysis on the impact of design parameters, providing useful information in optimizing the power and performance of the receiver at the early stage of design. The system-level simulation results with newer device parameters reveal that, although the power consumption of the ADC-based receiver may not comparable to the receivers with analog equalizers yet, they will become more attractive as the fabrication technology continues to scale as power consumption of digital equalizer scales well with process.

• Korean Journal of Computational Design and Engineering
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• v.4 no.4
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• pp.318-326
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• 1999

Recently, electronic systems including computers have been rapidly shrinking in size while at the same time the complexity and the capability of these systems continue to grow/sup [1]/. Thus, system volumes have decreased as system power has increased, resulting in dramatic increases in system heat density. The high temperature of the computer system is considered as the major reason for low performance and shortening life of the product. It is necessary to solve this problem due to the heat density increased and to develop the design skill of the computer cabinet according to miniaturization. M4500 desk-top computer was selected for analyzing the thermal management inside cabinet. The cabinet volume, the configuration of the heating devices, the size and location of air ventilation, and the fan selection have been investigated as the important parameters to find out an optimal cabinet design. The objectives of this project were to analyze which design parameters would affect cooling performance by thermal strategy, to design an optimal model, and to measure the temperatures of the main parts to confirm the effect of the thermal design. The temperatures of each part of the optimal model were compared with those of the existing model. As a result. the volume of this miniaturized model was about 16% smaller than that of M4500 without any change in operating performance.

• Journal of IKEEE
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• v.21 no.4
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• pp.331-337
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• 2017

In this paper, we present the design of a 20MHz bandwidth 3rd-order continuous-time low-pass sigma-delta modulator with low-noise and low-power consumption. The bandwidth of the system is sufficient to accommodate LTE and other wireless network standards. The 3rd-order low-pass filter with feed-forward architecture achieves the low-power consumption as well as the low complexity. The system uses 3bit flash quantizer to provide fast data conversion. The current-steering DAC achieves low-power and improved sensitivity without additional circuitries. Cross-coupled transistors are adopted to reduce the current glitches. The proposed system achieves a peak SNDR of 65.9dB with 20MHz bandwidth and power consumption of 32.65mW. The in-band IM3 is simulated to be 69dBc with 600mVp-p two tone input tones. The circuit is designed in a 0.18-um CMOS technology and is driven by 500MHz sampling rate signal.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.7
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• pp.515-520
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• 2014

In this paper, the protograph-based block low density parity check (LDPC) code, which improves the performance and reduces the encoder/decoder complexity than the conventional Digital Video Broadcasting Satellite Second Generation (DVB-S2) LDPC code used for the marine satellite communication, is proposed. The computer simulation results verify that the proposed protograph-based LDPC code has the better performance in both the bit error rate (BER) and the frame error rate (FER) than the conventional DVB-S2 LDPC code. Furthermore, by analyzing the encoding and decoding computational complexity, we show that the protograph-based block LDPC code has the efficient encoder/decoder structure.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.28-38
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• 2013

In this paper, we propose a improved turbo equalizer which generates a feedback signal through a simple calculation to improve performance in single carrier system with the LMS(least mean square) algorithm based equalizer and LDPC(low density parity check) codes. LDPC codes can approach the Shannon limit performance closely. However, computational complexity of LDPC codes is greatly increased by increasing the repetition of the LDPC codes and using a long parity check matrix in harsh environments. Turbo equalization based on LDPC code is used for improvement of system performance. In this system, there is a disadvantage of very large amount of computation due to the increase of the repetition number. To less down the amount of this complicated calculation, The proposed improved turbo equalizer adjusts the adoptive equalizer after the soft decision and the LDPC code. Through the simulation results, it's confirmed that performance of improved turbo equalizer is close to the SISO-MMSE(soft input soft output minimum mean square error) turbo equalizer based on LDPC code with the smaller amount of calculation.

• Journal of Communications and Networks
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• v.16 no.6
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• pp.639-644
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• 2014

In low-density parity-check (LDPC) coded multiple-input multiple-output (MIMO) communication systems, probabilistic information are exchanged between an LDPC decoder and a MIMO detector. TheMIMO detector has to calculate probabilistic values for each bit which can be very complex. In [1], the authors presented a class of linear block codes named low-density MIMO codes (LDMC) which can reduce the complexity of MIMO detector. However, this code only supports the outer-iterations between the MIMO detector and decoder, but does not support the inner-iterations inside the LDPC decoder. In this paper, a new approach to construct LDMC codes is introduced. The new LDMC codes can be encoded efficiently at the transmitter side and support both of the inner-iterations and outer-iterations at the receiver side. Furthermore they can achieve the design rates and perform very well over MIMO channels.