• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.686-689
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• 2003

This paper describes two kind of new concept for low power consumption for small area TFT-LCDs. First, the proposed analog buffer could reduce the static current by adopting new scheme. Second, new data driver structure reduced DC power consumption by reducing the number of operational amplifier (op-amp). As simulation results of Hspice, the quiescent current of proposed analog buffer is less than $0.8{\mu}A$ and the DC power consumption is reduced about $40{\sim}50%$ compared with conventional ones.

• 한국음향학회지
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• 제14권5호
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• pp.29-35
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• 1995

진동판 변위의 비선형적 운동에 의해 발생하는 스피커의 비선형왜곡은 음질을 열화시킨다. 이러한 비선형왜곡은 저주파 대역의 경우 주로 스피커의 지지부의 강성과 force factor의 비선형 특성에 의해 발생한다. 본 논문에서는 진동판 변위에 따라 변화하는 스피커의 비선형 강성과 비선형 force factor를 2차함수로 모델링하고 각각의 계수를 결정하는 방법에 대해 연구하였다. 진동판에 질량을 부가하여 동작점을 이동시키는 기계적인 방법을 사용하여 강성과 force factor 간의 커플링을 배제하였으며, 여러 동작점에서의 공진주파수를 측정함으로써 비선형 강성의 계수를 추출하였다. 비선형 force factor의 계수는 공진주파수에서 스피커에의 입력전압, 입력전류, 그리고 진동판 변위를 측정하여 얻은 그래프를 curve fitting 함으로써 구하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.72-75
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• 2003

For the analog output buffer in the data driver for large size and high resolution TFT-LCDs, we proposed operational amplifier (op-amp) which contains newly developed transconductance-boosted input stage which enables the low-power consumption and the high slew-rate. The slew-rate and the quiescent current of the proposed op-amp are $6.1V/{\mu}sec$ and $8{\mu}A$, respectively.

• 전자공학회논문지B
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• 제33B권7호
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• pp.70-79
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• 1996

To increase the functionality of the memories, previous studies have deifned faults models and proposed functional testing algorithms with low complexity. Although conventional testing depended strongly on functional (voltage) testing method, it couldn't detect short and open defects caused by gate oxide short and spot defect which can afect memory reliability. Therefore, IDDQ (quiescent power supply current) testing is required to detect defects and thus can obtain high reliability. In this paper, we consider resistive shorts on gate-source, gate-drain, and drain-source as well as opens in mOS FET and observe behavior of the memory by analyzing voltage at storge nodes of the memory and IDDQ resulting from PSPICE simulation. Finally, using this behavioral analysis, we propose a linear testing algorithm of complexity O(N) which can be applicable to both functional testing and IDDQ testing simultaneously to obtain high functionality and reliability.

• ETRI Journal
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• 제38권4호
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• pp.654-664
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• 2016

This paper presents a transformer-based reconfigurable synchronous boost converter. The lowest maximum power point tracking (MPPT)-input voltage and peak efficiency of the proposed boost converter, 20 mV and 88%, respectively, were achieved using a reconfigurable synchronous structure, static power loss minimization design, and efficiency boost mode change (EBMC) method. The proposed reconfigurable synchronous structure for high efficiency enables both a transformer-based self-startup mode (TSM) and an inductor-based MPPT mode (IMM) with a power PMOS switch instead of a diode. In addition, a static power loss minimization design, which was developed to reduce the leakage current of the native switch and quiescent current of the control blocks, enables a low input operation voltage. Furthermore, the proposed EBMC method is able to change the TSM into IMM with no additional time or energy loss. A prototype chip was implemented using a $0.18-{\mu}m$ CMOS process, and operates within an input voltage range of 9 mV to 1 V, and an output voltage range of 1 V to 3.3 V, and provides a maximum output power of 37 mW.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.1005-1008
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• 2007

In this study, an architecture for 262K-color TFT-LCD source driver. In this paper proposed the chip consumes smaller area and static current which is suitable for QVGA resolutions. In the conventional structures, all of them need large number of OPAMP buffers to drive the pixels, Therefore, highly resistive R-DACs are needed to generate gamma voltages to reduce the static current. In this study, our design only used two OPAMPs and low resistance RDACs without increasing the quiescent current. Thus, it was experted that chip would be more in consuming lower static power for longer battery lifetime. The source driver were implemented by the 3.3 V $0.35\;{\mu}m$ CMOS technology provided by TSMC. The area of the core OPAMP circuit was about $110\;{\mu}m\;{\times}\;150\;{\mu}m$ and that of the source driver was $880\;{\mu}m\;{\times}\;430\;{\mu}m$. As compared to the conventional structure, approximately 64.48 % in area was achieved.

• 대한전자공학회논문지SD
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• 제43권10호
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• pp.118-125
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• 2006

휴대용 전자제품의 증가에 따라 배터리의 사용 시간을 증가시키기 위한 파워 메니지먼트 회로의 설계는 매우 중요해지고 있다. 이에 따라 전원공급 시스템, 특히 파워 효율이 높은 스위칭 방식의 DC-DC 변환기의 필요성은 더욱 커지고 있다. 본 논문에서 제안된 새로운 에러 앰프는 고속으로 동작하는 DC-DC 컨버터를 위해 고성능의 구조를 구현하고 있다. 본 앰프는 높은 전력변환 효율을 위해 낮은 대기 전류를 갖지만, 큰 입력신호 구간에서는 충분한 전류를 공급할 수 있도록 설계되었다. 두 개의 비교기가 구현되어 큰 신호의 변화를 감지해서 여분의 전류 공급기를 턴-온 시켜서 필요한 전류를 공급해준다. 피드백 동작하는 DC-DC 컨버터의 특성상 다양한 동작 환경에서 시스템의 안정성을 보장하기 위해서는 여분의 전류의 양이 잘 조절되어야 한다. 시뮬레이션 결과는 시간 천이 반응에서 새로운 앰프가 기존의 앰프보다 뛰어난 성능향상을 얻을 수 있음을 보여준다.

• Journal of electromagnetic engineering and science
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• 제14권4호
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• pp.393-398
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• 2014

A highly efficient dual-mode linear CMOS stacked-FET power amplifier (PA) is implemented for 3G UMTS and 4G LTE handset applications. High efficiency is achieved at a backed-off output power ($P_{out}$) below 12 dBm by employing an active-bypass amplifier, which consumes very low quiescent current and has high load-impedance. The output paths between high- and low-power modes of the PA are effectively isolated by using a bypass switch, thus no RF performance degradation occurs at high-power mode operation. The fabricated 900 MHz CMOS PA using a silicon-on-insulator (SOI) CMOS process operates with an idle current of 5.5 mA and shows power-added efficiency (PAE) of 20.5%/43.5% at $P_{out}$ = 12.4 / 28.2 dBm while maintaining an adjacent channel leakage ratio (ACLR) better than -39 dBc, using the 3GPP uplink W-CDMA signal. The PA also exhibits PAE of 35.1% and $ACLR_{E-UTRA}$ of -33 dBc at $P_{out}$ = 26.5 dBm, using the 20 MHz bandwidth 16-QAM LTE signal.

• 천문학회보
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• 제40권1호
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• pp.80.1-80.1
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• 2015

We present a study of outflows on 24 embedded young stellar objects selected from the source list of the Dust, Ice, and Gas in Time (DIGIT) Herschel key program. To study the relation between the CO outflows observed in low-J transitions and the properties of protostars more consistently with a homogeneous data set, we mapped the CO outflows of the selected targets in the J = 1-0 and J = 2-1 lines with two Korean telescopes (SRAO and TRAO). We compare CO outflow force ($F_{CO}$) with the bolometric luminosity, ($L_{bol}$) bolometric temperature, and the FIR molecular line luminosities of CO, $H_2O$, OH, and [O I] detected by the Herschel-PACS observations. We find that $F_{CO}$ of J = 1-0 is greater than that of 2-1 by a factor of ~ 2. The well known correlation between $F_{CO\;2-1}$ and $L_{bol}$ is not very evident in our sample as a whole, but they show a rather strong correlation when IRAM 04191+1522 is excluded. IRAM 04191+1522 has relatively high $F_{CO\;2-1}$ in spite of its low $L_{bol}$. This object is a well-known VeLLO, which is believed in the quiescent phase of the episodic mass accretion in the embedded stage. $L_{bol}$ traces a current accretion, but $F_{CO\;2-1}$ traces accretion happened long ago. Therefore, the low-$L_{bol}$ with the high-$F_{CO\;2-1}$ can be explained by the episodic accretion. $F_{CO\;2-1}$ shows little correlation with individual FIR line luminosities of CO, $H_2O$, OH, while [O I] and total FIR line luminosity seem to have correlations with $F_{CO\;2-1}$. This result is interpreted as the accretion energy deposits on species differently depending on shock properties, but the total FIR line luminosity sums the total accretion energy dispersed to different species.

• 전자공학회논문지SC
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• 제37권2호
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• pp.29-36
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• 2000

본 논문에서는 트랜지스터 동작영역에 독립적인 일정 트랜스컨덕턴스 rail-to-tail 입력회로 및 AB-급 출력회로를 갖는 2단 연산증폭기를 제시한다. rail-to-rail 입력회로는 추가 NMOS 및 PMOS 차동 입력단 구조를 사용하여, 전체 동상 입력 전압에서 항상 일정한 트랜스컨덕턴스를 갖도록 하였다. 이러한 입력단 회로는 기존 MOS의 정확한 전류-전압 관계식을 사용하지 않고, 트랜지스터의 동작영역에서, 즉 강 반전 및 약 반전, 독립적인 새로운 광역 선형 전류관계를 제안한다. 본 논문에서 제안한 입력단 회로를 SPICE를 사용하여 모의실험 결과, 전체 동상 입력 전압에 대해서 4.3%의 변화율이 나타남을 검증하였다. AB-급 출력단 회로는 공급 전압원에 독립적인 일정한 동작 전류값을 갖고, 출력 전압은 Vss+0.1에서 Vdd-0.15까지 구동하는 전압 특성을 나타내었다. 또한 출력단은 AB-급 궤환 제어 방식을 사용하여 저전압에서 동작 할 수 있다. 전체 연산 증폭기의 단일-이득 주파수 및 DC 전압이득 변화율은 각각 4.2% 및 12%로 나타냈다.