• Journal of Power Electronics
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• v.17 no.5
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• pp.1137-1149
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• 2017

In order to reduce the cost, improve the efficiency and simplify the complicated control of existing isolated LED drivers, an improved boundary conduction mode (BCM) Buck ac-dc light emitting diode (LED) driver with extended output voltage and low total harmonic distortion is proposed. With a coupled inductor winding and a stacked output, its output voltage can be elevated to a much higher value when compared to that of the conventional Buck ac-dc converter, without sacrificing the input harmonics and power factor. Therefore, the proposed Buck LED driver can meet the IEC61000-3-2 (Class C) limitation and has a low THD. The operating principle of the topology and the design methodology of the ac-dc LED driver are presented. A 150 W ac-dc prototype was built in the laboratory and it shows that the input current harmonics meet the lighting standard. In addition, the THD is less than 16% at a typical ac input. The peak efficiency is higher than 96.5% at a full load and a normal input.

• Journal of Power Electronics
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• v.10 no.1
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• pp.9-13
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• 2010

This paper proposes an input-series-output-parallel connected ZVS full bridge converter with interleaved control for photovoltaic power conditioning systems (PV PCS). The input-series connection enables a fully modular power-system architecture, where low voltage and standard power modules can be connected in any combination at the input and/or at the output, to realize any given specifications. Further, the input-series connection enables the use of low-voltage MOSFETs that are optimized for a very low RDSON, thus, resulting in lower conduction losses. The system costs decrease due to the reduced current, and the volumes of the output filters due to the interleaving technique. A topology for a photovoltaic (PV) dc/dc converter that can dramatically reduce the power rating and increase the efficiency of a PV system by analyzing the PV module characteristics is proposed. The control scheme, consisting of an output voltage loop, a current loop and input voltage balancing loops, is proposed to achieve input voltage sharing and output current sharing. The total PV system is implemented for a 10-kW PV power conditioning system (PCS). This system has a dc/dc converter with a 3.6-kW power rating. It is only one-third of the total PV PCS power. A 3.6-kW prototype PV dc/dc converter is introduced to experimentally verify the proposed topology. In addition, experimental results show that the proposed topology exhibits good performance.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.10
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• pp.1432-1441
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• 2012

In this study, an improved LCCT(Inductor-Capacitor-Capacitor-Trans) Z-source inverter(Improved LCCT ZSI) with characteristics of Quasi Z-source inverter(QZSI) and LCCT Z-source inverter(LCCT ZSI) is proposed. The proposed inverter can also reduce the voltage stress and input current/capacitor voltage ripples compared with conventional LCCT ZSI and Quasi ZSI. A two winding trans in Z-impedance network of the conventional LCCT ZSI is replaced by a three winding trans in the proposed inverter. To verify the validity of the proposed inverter, a DSP controlled hardware was made and PSIM simulation was executed for each method. Comparing the current and voltage ripples of each method under the condition of input DC voltage 70[V] and output AC voltage 76[Vrms], the input current and capacitor voltage ripple factors of the proposed inverter were low as 11[%] and 1.4[%] respectively. And, for generation of the same output AC voltage of each method, voltage stress of the proposed inverter was low as 175[V] under the condition of duty ratio D=0.15. As mentioned above, we could know that the proposed inverter have the characteristics of low voltage stress, low ripple factor and low operation duty ratio compared with the conventional methods. Finally, the efficiency according to load change/duty ratio and the transient state characteristics were discussed.

• Journal of Ocean Engineering and Technology
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• v.28 no.6
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• pp.540-545
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• 2014

Multipass self-shielded flux cored arc welding with different heat inputs (1.3–2.0 kJ/mm) was conducted to determine the effects of the heat input on the proportion of the reheated region, impact toughness, and diffusible hydrogen content in the weld metal. The reheated region showed twice the impact toughness of the as-deposited region because of its fine grained ferritic-pearlitic microstructure. With decreasing heat input, the proportion of the reheated region in the weld metal became higher, even if the depth of the region became shallower. Accordingly, the greatest impact toughness, 69 J at −40℃, was obtained for the lowest heat input welding, 1.3 kJ/mm. Irrespective of the heat input, little difference was observed in the hardness and diffusible hydrogen content in the weld metal. This result implies that low heat input welding with 1.3 kJ/mm can be performed to obtain a higher proportion of reheated region and thus greater impact toughness for the weld metal without the concern of hydrogen cracking.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.646-649
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• 1999

A new isolated boost dc to dc convertor suitable for a low input voltage application is proposed. The proposed convertor features the low switch current stresses, the wide input voltage range operation, and the inherent inrush current protection characteristics, essential to design a low to high voltage conversion circuit. A comparative analysis and experimental results are presented to show the validity of the proposed convertor.

• Journal of Power Electronics
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• v.12 no.1
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• pp.83-87
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• 2012

Input-series-output-parallel (ISOP) modular converters consisting of multiple modular DC/DC converters can enable low voltage rating switches for use in high voltage input applications. In this paper, an input voltage sharing control strategy for input-series-output-parallel (ISOP) full-bridge (FB) DC/DC converters is proposed. By sensing the difference in the input current of two modules, the system can achieve input voltage sharing for DC-DC modules. The effectiveness of the proposed control strategy is verified by simulation and experimental results obtained with a 200w-50kHz prototype.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.6
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• pp.853-856
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• 2021

In this paper, a low noise amplifier having high gain and low noise by using input and inter stage matching circuits has been designed. A current-reused two-stage common-source topology is adopted, which can obtain high gain and low power consumption. Deterioration of noise characteristics according to the source inductive degeneration matching is compensated by adopting additional matching circuits. Moreover trade-offs among noise, gain, linearity, impedance matching, and power dissipation have been considered. In this design, 0.18-mm CMOS process is employed for the simulation. The simulated results show that the designed low noise amplifier can provide high power gain and low noise characteristics.

• Journal of Power Electronics
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• v.15 no.3
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• pp.644-651
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• 2015

This paper introduces a novel digital one cycle control (DOCC) boost power factor correction (PFC) converter. The proposed PFC converter realizes the FPGA-based DOCC control approach for single-phase PFC rectifiers without input voltage sensing or a complicated two-loop compensation design. It can also achieve a high power factor and the operation of low harmonic input current ingredients over universal loads in continuous conduction mode. The trailing triangle modulation adopted in this approach makes the acquisition of the average input current an easy process. The controller implementation is based on a boost topology power circuit with low speed, low-resolution A/D converters, and economical FPGA development board. Experimental results demonstrate that the proposed PFC rectifier can obtain a PF value of up to 0.999 and a minimum THD of at least 1.9% using a 120W prototype.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.4
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• pp.25-32
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• 1997

In this paper, we propose an adaptive BTC algorithm using the characteristics of the error signals. The BTC algorithm has a avantage that it is low computational complexity, but a disadvantage that it produces the ragged edges in the reconstructed images for th esloping regions beause of coding the input with 2-level signals. Firstly, proposed methods classify the input into low, medium, and high activity blocks based on the variance of th einput. Using 1-level quantizer for low activity block, 2-level for medium, and 4-level for high, it is adaptive methods that reduce bit rates and the inherent quantization noises in the 2-level quantizer. Also, in case of processing high activity block, we propose a new quantization level allocation algorithm using the characteristics of the error signals between the original signals and the reconstructed signals used by 2-level quantizer, in oder that reduce bit rates superior to the conventional 4-level quantizer. Especially, considering the characteristics of input block, we reduce the bit rates without incurrng the visual noises.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.252-256
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• 2006

A low-power ECC check bit generator is presented with competent DRAM implementation with minimal speed loss, area overhead and power consumption. The ECC used in the proposed scheme is a variant form of the minimum weight column code. The spatial and temporal correlations of input data are analyzed and the input paths of the check bit generator are ordered for the on-line adaptable power savings up to 24.4% in the benchmarked cases. The chip size overhead is estimated to be under 0.3% for a 80nm 1Gb DRAM implementation.